CS 354 - Digital Systems Design (Section 01)

Spring-2025

Catalog data: An introduction to the analysis and design of digital systems in terms of logical and sequential networks. Various minimization techniques are studied.

Prerequisites: CS 254 and (MATH 217 or MATH 218)

Course Description: This course teaches how to design digital circuits at gate level. It includes theoretical material on Boolean algebra and finite state machines, which are part of the fundamental Computer Science theory. Students analyze and design combinational and sequential circuits by using modern approaches to hardware simulation such as the Hardware Description Language. They use hierarchical approaches to create the basic components of the computer such as decoders, adders, registers and memories. At the end, students use their knowledge to design a simple central processing unit (CPU).

Course Learning Outcomes (CLO):

1. Understand the basics of Boolean algebra
2. Use minimization techniques to implement Boolean functions by logic gates
3. Implement basic combinational circuits as adders, multiplexers, encoders and decoders
4. Understand the basics of synchronous sequential logic and finite state machines
5. Implement clocked sequential circuits as registers, counters and memory devices
6. Use a Hardware Description Language (HDL) to design and implement digital circuits
7. Design and implement simple ALU and CPU

• SO-2: Design, implement, and evaluate a computing-based solution to meet a given set of computing requirements in the context of the program s discipline (supported by CLO's 5, 6, 7).
• SO-6: Apply computer science theory and software development fundamentals to produce computing-based solutions (supported by CLO's 1, 2, 3, 4).

Required software:

• Icarus Verilog - freeware, available for download from http://bleyer.org/icarus/ and online at https://www.jdoodle.com/execute-verilog-online.
• Digital Works (optional) - freeware, http://www.cs.ccsu.edu/~markov/ccsu_courses/CS354/Digital.exe

Course Expectations for Out-of-Class Work: To succeed in this 3-credit class, it is expected that you commit a total of 12 hours per week to master the course material. This includes 2.5 hours of lecture time and an additional 9.5 hours dedicated to independent study and coursework. This time commitment aligns with the expectations set by the Computer Science department for major courses and adheres to university policies. Recognizing that dedicating this amount of time outside the classroom is a significant commitment, it is nevertheless necessary for success. Please plan your course load accordingly.

Assignments and tests: Reading and problem assignments are listed below. Problems are to be done, but do not need to be handed in. Some of the problems will be worked in class. There will be three tests and a final exam. The tests will include questions from the textbook, questions from the lectures, and questions from the assigned projects.

Projects: There will be three projects requiring the use of the Verilog Hardware Description Language to implement and simulate digital circuits. The projects with their due dates are listed below in the class schedule (the project descriptions will be available in Blackboard). All projects must be submitted through the course page in Blackboard at https://ccsu.blackboard.com/.

Grading: The final grade will be based on projects (45%), tests (30%), and the final exam (25%), and will be affected by classroom participation, conduct and attendance. All grades will be availabe in Blackboard. The letter grades will be calculated according to the following table:

A	A-	B+	B	B-	C+	C	C-	D+	D	D-	F
94-100	90-93	87-89	84-86	80-83	77-79	74-76	70-73	67-69	64-66	60-63	0-59

Unexcused late submission policy: Assignments submitted more than two days after the due date will be graded one letter grade down. Projects submitted more than a week late will receive two letter grades down. No submissions will be accepted more than two weeks after the due date.

Honesty policy: The CCSU honor code for Academic Integrity is in effect in this class. It is expected that all students will conduct themselves in an honest manner and NEVER claim work which is not their own. Violating this policy will result in a substantial grade penalty, and may lead to expulsion from the University. You may find it online at http://web.ccsu.edu/academicintegrity/. Please read it carefully.

Students with disabilities: Central Connecticut State University (CCSU) is dedicated to ensuring equal access to academic programs and services in accordance with the Americans with Disabilities Act (ADA) and Section 504 of the Rehabilitation Act. Students with documented disabilities or temporary impairments who require accommodations are encouraged to contact the Office of Accessibility Services (OAS) at 860-832-1952 or via email at accessibilityservices@ccsu.edu. For more information on the registration process for accommodations, please visit the Accessibility Services website at https://www.ccsu.edu/accessibility/. Once accommodations are approved, it is strongly recommended that students discuss their needs with professors at the start of each semester to ensure mutual understanding. Please note that accommodations must be requested each semester and cannot be applied retroactively.

University policies: The university policies are available at https://www.ccsu.edu/sites/default/files/document/SyllabusStatementonDiscriminationandHarassment.pdf. Please read them carrefuly.

Tentative schedule of classes, assignments and tests

1. Jan 22: Basic components of the computer and its implementation: from instructions to gates. Run the 4-bit CPU (download it from Blackboard and use Digital Works). Read Chapter 1.
2. Jan 27: Boolean algebra: basic definitions, theorems and properties
3. Jan 29: Boolean functions
4. Feb 3: Canonical and standard form of Boolean functions
5. Feb 5: Logic operations and logic gates
6. Feb 10: Review of Chapter 2
7. Feb 12: Test 1 (Chapter 2, max. grade: 10 pts)
8. Feb 19: Simplification of Boolean functions: the map method
9. Four variable maps, don't-care conditions
10. NAND and NOR implementation of boolean functions, other implementations of boolean functions
11. Review of Chapter 3. Problems: 3.1 - 3.13, 3.15 - 3.17, 3.18 - 3.23, 3.27 - 3.30.
12. Test 2 (Chapters 2 and 3, max. grade: 10 pts.)
13. Combinational logic: analysis, design, adders, subtractors, decimal adder
14. Basics of HDL and using Verilog, Project 1 posted
15. Verilog Lab: half-adder, full adder, incrementer using 4 half-adders, 4-bit adder.
16. Decoders and multiplexers
17. Read-only memory and PLA
18. Review of Combinational Logic, ROM, and PLA. Problems: 4.9, 4.10, 4.11, 4.23, 4.25, 4.27, 4.28, 4.31, 4.32, 4.33, 7.18, 7.19, 7.20, 7.28.
19. Project 1 due (max. grade: 15 pts.)
20. Test 3 (Chapter 4, ROM, and PLA, max. grade: 10 pts.). See Test 3 Practice Problems in Blackboard.
21. Using HDL to design combinational circuits
22. Designing an ALU. Project 2 posted
23. Synchronous sequential logic: flip-flops
24. Analysis of clocked sequential circuits: finite state machines
25. Project 2 due (max. grade: 15 pts.)
26. Designing clocked sequential circuits
27. Designing a CPU, Project 3 posted
28. Register and counters. Review of Synchronous Sequential Circuits
29. Extra credit Quiz (2-level NAND, decorder, ROM and PLA implementations, Synchronous Sequential Circuits). Online timed test (2 hours).
30. Project 3 due (max. grade: 15 pts.)
31. Review for Final Exam
32. Final Exam (max. grade: 25 pts.)

Boolean algebra: basic definitions, theorems and properties

Lecture Notes:

A little history: George Boole and Boolean Logic

Axioms of Boolean algebra (set of elements B, two binary operators: + and .):

1. Closure
• w.r.t. +
• w.r.t. .
2. Identity element
• w.r.t. + denoted by 0: x+0=0+x=x
• w.r.t. . denoted by 1: x.1=1.x=x
3. Commutative law
• w.r.t. +: x+y=y+x
• w.r.t. .: x.y=y.x
4. Distributive law
• over +: x.(y+z)=(x.y)+(x.z)
• over .: x+(y.z)=(x+y).(x+z)
5. Complement: for every x there exists x', such that:
• x+x'=1
• x.x'=0
6. There exist at least two distinct elements x, y in B.

Defining a boolean algebra:

1. Show the elements of B
2. Show the rules of the operators + and .
3. Show that the axioms are satisfied
4. Example of a Boolean Algebra: For any set A, the subsets of A form a Boolean algebra under the operations of union, intersection and complement.

Binary logic (two-valued Boolean algebra):

1. B={0,1}
2. +  =  OR, . = AND, ' = NOT (truth tables)
3. Closure
4. Identity: 0 for + and 1 for .
5. Commutative law: see the truth tables
6. Distributive law: show by a truth table
7. Complement: show by a truth table and by the complement table
8. There are two distinct elements in B: 0 and 1

Basic theorems

1. x+x=x, x.x=x
2. x+1=1, x.0=0
3. (x')'=x (involution)
4. x+(y+z)=(x+y)+z, x.(y.z)=(x.y).z (associativity)
5. (x+y)'=x'.y', (x.y)'=x'+y' (DeMorgan's law)
6. x+xy=x, x.(x+y)=x (absorption)

Boolean functions

Lecture Notes:

• algebraic expression - infinite number of expressions for a single boolean function.
• truth table - unique representation.

F1 = xyz'
F2 = x + y'z
F3 = x'y'z + x'yz + xy'
F4 = xy' + x'z
 

x     y     z	F1  F2  F3  F4
0     0     0  0     0     1  0     1     0  0     1     1  1     0     0  1     0     1  1     1     0  1     1     1	0   0   0   0   0   1   1   1  0   0   0   0   0   0   1   1   0   1   1   1   0   1   1   1   1   1   0   0   0   1   0   0

Implementing a Boolean function in Logic Gates (AND, OR, NOT)

• Using the algebraic form:
• literal: an input to a logic gate
• term: logic gate
• term and literal minimization
• Using truth table - first transform into algebraic form, sum of products

1. truth tables for result and carryout
2. transform into sum of products
3. build the logic diagram

• minimization of literals
• complement of a function, DeMorgan's theorem for more than two variables (dual of the function and complement each literal):
• (A+B+C+D+...)' = A'B'C'D'+...
• (ABCD...)' = A'+B'+C'+D'+...

1. x+x'y = (x+x')(x+y) = 1(x+y) = x+y

2. x(x'+y) = xx'+xy = 0+xy = xy

3. x'y'z+x'yz+xy' = x'z(y'+y)+xy' = x'z+xy'

4. xy+x'z+yz = xy+x'z+yz(x+x') = xy+x'z+xyz+x'yz = xy(1+z)+x'z(1+y) = xy+x'z

5. (x+y)(x'+z)(y+z) = (x+y)(x'+z)

Canonical and standard form of Boolean functions

Lecture Notes:

Minterms and maxterms for three variables

x   y   z	Minterms	Maxterms
0   0   0	x'y'z'        m0	x + y + z      M0
0   0   1	x'y'z         m1	x + y + z'     M1
0   1   0	x'yz'         m2	x + y'+ z      M2
0   1   1	x'yz          m3	x + y'+ z'     M3
1   0   0	xy'z'         m4	x'+ y + z      M4
1   0   1	xy'z          m5	x'+ y + z'     M5
1   1   0	xyz'          m6	x'+ y'+ z      M6
1   1   1	xyz           m7	x'+ y'+ z'     M7

2. Representing Boolean functions (truth table) by a sum of minterms or by a product of maxterms
 

x     y     z	F     F'
0     0     0   0     0     1   0     1     0   0     1     1   1     0     0   1     0     1   1     1     0   1     1     1	0     1  1     0   0     1   0     1   1     0   0     1  0     1   1     0

F = x'y'z + xy'z' + xyz = m1 + m4 + m7

F'= x'y'z' + x'yz' + x'yz + xy'z + xyz'

(F')' = F = (x+y+z)(x+y'+z)(x+y'+z')(x'+y+z')(x'+y'+z) = M0.M2.M3.M5.M6

Alternative notation: F = Sum(1,4,7), F = Prod(0,2,3,5,6)

3. Canonical form (sum of minterms or product of maxterms) of Boolean functions

• We have  2^(2^n) functions of n variables.
• Transforming into sum of minterms:
• From algebraic form directly (using distributive law and ANDing (x+x') if x is missing).
• Example: F = a + b'c = ... = Sum(1,4,5,6,7)
• Using a truth table
• Transforming into product of maxterms: using distributive law and ORing xx'if x is missing).
• Example: F = xy + x'z = ... = Prod(0,2,4,5)

F=Sum(1,4,7)
F'=Sum(0,2,3,5,6)
F=(F')'=(Sum(0,2,3,5,6))'=Prod(0,2,3,5,6)

4. Standard form - sum of products or product of sums not necessarily containing all variables in the individual terms

Logic operations and logic gates

Lecture Notes:

2. Algebraic forms of the 16 functions of 2 variables (pdf)

3. Digital Logic gates and their implementation:

1. AND
2. OR
3. Inverter
4. Buffer
5. NAND
6. NOR
7. XOR
8. XNOR

• AND and OR: simple cascading
• 3-input NOR and NAND: not associative, change the definition to (x+y+z)' and (xyz)'
• Multiple input XOR and XNOR: associative, change the definition to "odd number of 1's"

• AND, OR, and NOT gates
• AND and NOT gates
• OR and NOT gates
• NAND gates
• NOR gates

Review of Chapter 2

Lecture Notes:

1. Boolean algebra: basic definitions, theorems and properties
2. Boolean functions. Algebraic simplification
3. Canonical and standard form of Boolean functions.
4. Logic operations and logic gates
5. Implementation of the Boolean functions in logic gates:
• AND, OR, NOT
• NAND
6. Example 1. Function F is defined by the following truth table:

• Obtain the boolean expressions of F as a sum of minterms and a product of maxterms
• Simplify both forms of F to minimal number of terms
• Implement the simplified function by using:
• AND, OR, and NOT gates
• AND and NOT gates
• OR and NOT gates
• NAND gates
7. Example 2:
• Show the boolean function implemented in the follwing diagram.

• Obtain the canonical form of the function as a sum of minterms by algebraic transformations.
• Obtain the canonical form of the function as a product of maxtermss by algebraic transformations.

Simplification of Boolean functions - the map method

Lecture Notes:

Two-variable map (properties)
 

m0	m1
m2	m3

x \ y	0	1
0	x'y'	x'y
1	xy'	xy

Examples:

xy

	1

x+y = x(y+y')+y(x+x') = xy+xy'+yx+yx' = xy+xy'+yx'

	1
1	1

(x+y)' = x'y'

1

Three-variable map (note the sequence)
 

m0	m1	m3	m2
m4	m5	m7	m6

x \ yz	00	01	11	10
0	x'y'z'	x'y'z	x'yz	x'yz'
1	xy'z'	xy'z	xyz	xyz'

Example: a + b'c = ... = Sum(1,4,5,6,7)
 

	1
1	1	1	1

2. Simplification using maps (minimization of the number of terms) 3-variable map

• Adjacent squares (including m0 and m2, m4 and m6). Example: Sum(3,4,6,7) = xz'+yz
• 1 square - a term with 3 literals
• 2 adjacent squares - a term with 2 literals
• 4 adjacent squares - a term with 1 literal
• 8 adjacent squares - constant function 1
• Using adjacent squares more than once. Example: Sum(0,2,4,5,6) = z'+xy'
• Using a standard form (sum of product) - representing a product as adjacent squares. Example: x'z+x'y+xy'z+yz (mapping)

x'y+x'y' =  m0+m1 = x' = M2.M3 = x'
 

1	1
0	0

Example: F(x,y,z) = Sum(0,1,2,5)

Four variable maps, don't-care conditions

Lecture Notes:

Example 1: Sum(0,1,2,4,5,6,8,9,12,13,14) = y'+w'z'+xz'

wx\yz	00	01	11	10
00	1	1		1
01	1	1		1
11	1	1		1
10	1	1

Example 2: Sum(0,1,2,6,8,9,10) = x'y'+x'z'+w'yz'

wx\yz	00	01	11	10
00	1	1		1
01				1
11
10	1	1		1

2. A systematic approach to combining adjacent squares - prime implicants (max number of squares)

Example 3: Sum(0,2,3,5,7,8,9,10,11,13,15)

wx\yz	00	01	11	10
00	1		1	1
01		1	1
11		1	1
10	1	1	1	1

1. Essential prime implicant for m5, m7, m13, m15: xz
2. Essential prime implicant for m0, m2, m8, m10: x'z'
3. Prime implicants for m3, m9, m11: yz, x'y, wz, wx'

3. Incompletely specified functions (don't-care conditions)
Example: F(a,b,c,d) = Sum(1,3,7,11,15), D(a,b,c,d) = Sum(0,2,5)

4. The tabulation method (optional)

4.1. Determination of prime implicants

Example 1: F = Sum(0,1,2,8,10,11,14,15)
 

w x y z	w x y z	w x y z
0   0 0 0 0 * ---------------  1   0 0 0 1 *   2   0 0 1 0 *   8   1 0 0 0 * ---------------  10  1 0 1 0 *  ---------------  11  1 0 1 1 *   14  1 1 1 0 *  ---------------  15  1 1 1 1 *	0,1    0 0 0 -   0,2    0 0 - 0 *   0,8    - 0 0 0 * ------------------  2,10   - 0 1 0 *   8,10   1 0 - 0 *  ------------------  10,11  1 0 1 - *  10,14  1 - 1 0 * ------------------  11,15  1 - 1 1 *  14,15  1 1 1 - *	0,2,8,10     - 0 - 0   0,8,2,10     - 0 - 0 ----------------------  10,11,14,15  1 - 1 -   10,14,11,15  1 - 1 -

F = w'x'y' + x'y' + wy

1. Compare to the map method (same implicants)
2. Decimal comparison (difference by a power of 2)
3. Example 2: F = Sum(1,4,6,7,8,9,10,11,15)
• Tabulation: F=x'y'z + w'xz' + w'xy + xyz + wyz + wx'
• Map: F=x'y'z + w'xz' + xyz + wx'

1. Include all essential prime implicants (covering a single term): (1,9), (4,6), (8,9,10,11)
2. Choose minimal number of prime implicants: (7,15)

NAND and NOR implementation of boolean functions, other implementations of boolean functions

Lecture Notes:

• Useful graphic symbols:
• NAND or Invert-OR
• NOR or Invert-AND
• NAND-NAND (two level) implementation of Boolean functions. Example: F=xy+x'y'z'+x'yz'
1. Simplify the function (sum of products)
2. A NAND gate for each term (first level)
3. A single NAND gate at the second level with inputs coming from the outputs of the first level NAND's
• NOR-NOR implementation - the dual of the NAND-NAND
• Example: F=xy+x'y'z'+x'yz'. Implement F and F' by NAND-NAND, NOR-NOR and inverted the output.
• Multilevel NAND implementation. Example: F=(AB'+A'B)(C+D')
1. Create an AND-OR multilevel implementation
2. Convert AND gates into NAND gates by inserting bubbles along the output.
3. Convert OR gates into NAND gates  (inserting bubbles at the inputs if necessary)
4. Remove all pairs of bubbles along the same line.
5. Replace the remaining bubles with one-input NAND gates
• Multilevel NOR implementation. Example: F=(AB'+A'B)(C+D')
• Nondegenerate forms of two level implementations:
• AND-OR, OR-AND
• NAND-NAND
• NOR-NOR
• NAND-AND, AND-NOR (AND-OR-INVERT)
• OR-NAND, NOR-OR (OR-AND-INVERT)
• XOR function (difference)
• Properties
• AND-OR-NOT implementation
• NAND implementation
• Odd function
• XOR with more than two inputs
• implementation by cascading XOR's
• Parity checking

Basics of HDL and using Verilog and Digital Works

Lecture Notes:

• Download or run Digital Works (freeware, http://www.cs.ccsu.edu/~markov/ccsu_courses/CS354/Digital.exe)
• Create a Macro for XOR (Macro Tags, Template Editor and Associate with Tag)
• Use the XOR marco to design the circiut (Embed Macro): my_xor.zip
• Digital Works Help
• Getting Started with Digital Works
• Designing a macro in Digital Works

1. Modules
2. Gate-level description
3. Test bench simulation
4. Example: implement a 3-input XOR,  F(A,B,C) = A XOR B XOR C


// HDL Example (hierarchical design)
//----------------------------------
module my_xor(A,B,C);
   input A,B;
   output C;
   wire x,y,z;
   nand g1 (x,A,B),
        g2 (y,A,x),
        g3 (z,x,B),
        g4 (C,y,z);
endmodule

module my_xor3(A,B,C,D);
   input A,B,C;
   output D;
   wire x;
   my_xor XOR1 (A,B,x),
          XOR2 (x,C,D);
endmodule

module test_xor3;
   reg A,B,C; // reg for inputs
   wire D;    // wire for outputs
   my_xor3 xor3(A,B,C,D); // Instantiate my_xor3
   initial
     begin
       $monitor("%1d %b %b %b %b",$time,A,B,C,D);
       $display("  A B C D");
          A=0; B=0; C=0;
       #1 A=0; B=0; C=1;
       #1 A=0; B=1; C=0;
       #1 A=0; B=1; C=1;
       #1 A=1; B=0; C=0;
       #1 A=1; B=0; C=1;
       #1 A=1; B=1; C=0;
       #1 A=1; B=1; C=1;
     end
endmodule

5. Icarus Verilog (http://bleyer.org/icarus/).
• Note about installation: use the latest stable release (iverilog-0.9.7_setup.exe) and don't use folder names that include spaces, like Program Files.
• Online compiler: https://www.jdoodle.com/execute-verilog-online
• Write the Verilog source file: 4-bit-adder.vl
• Compile:
C:\CS354\HDL>iverilog 4-bit-adder.vl
• Run:
C:\CS354\HDL>vvp a.out
0000 0000 0 0000 0                  0
0000 0001 1 0010 0                  10
0001 0111 1 1001 0                  20
1111 0000 1 0000 1                  30

Combinational logic: analysis, design, adders, subtractors, decimal adder

Lecture Notes:

1. Two types of logic circuits:
• Combinational logic (set of m Boolean functions of n variables), example: 7-segment LED display.
• Sequential (output are determined not only by the inputs, but also by internal states).
2. Analysis of digital circuits:
• Combinational or sequential? (no memory elements, no feedback)
• Determine the Boolean function
3. Design procedure
• Determine the number of inputs and outputs
• Derive the truth table
• Simplify the boolean function
• Draw the logic diagram
• Code conversion example: 3-bit 2's complementer
4. Adders: 0+0=0, 0+1=1, 1+0=1, 1+1=10.
• 1-bit half-adder: add two bits (x, y) and produce sum (S) and carry (C).
• Separate circuit implementation: C=xy, S=xy'+x'y (XOR).
• Sharing components implementations: C=xy, S=(C+x'y')'; C=(x'+y')', S=(x+y)(x'+y').
• 1-bit full-adder: add two bits and the carry from previous digit (x, y, z) and produce sum (S) and carry (C).
• Direct implementation: truth table, sum of minterms (C=xy+xz+yz, S=x'y'z+x'yz'+xy'z'+xyz).
• Cascading two half adders: S = add(add(x,y),z), C = C1+C2.
• Hierarchical design: 4-bit adder by cascading 4 1-bit adders.
5. Subtractors: 0-0=0(B=0), 0-1=1(B=1), 1-0=1(B=0), 1-1=0(B=0).
• Half-subtractor: subtract two bits and produce result and borrow.
• Full-subtractor: subtract two bits taking into account a borrow from the previous digit.
6. N-bit binary adder
• direct implementation: truth table with 2^(n+1) rows
• hierarchical implementation: cascading n 1-bit adders (serial, parallel)
7. Adder-subtractor (two's complement numbers)
8. Carry propagation (delay) and carry look-ahead logic
• carry propagate:  Pi = Ai xor Bi
• carry generate: Gi = Ai.Bi
• carry look-ahead logic: Ci+1 = Gi + Pi.Ci
• 4-bit adder with carry look-ahead: 4 half adders (xor, and) + carry look-ahead + 4 xor's
9. Detecting overflow:
• Overflow(A3, B3, S3)
• Overflow(C3,C4) = C3 XOR C4.
10. BCD adder: 4-bit adder + correction logic (if sum>1010 then add 0110 and produce decimal carry)

Decoders, encoders and multiplexers

Lecture Notes:

2. NAND implementation: inverted outputs and  enable (E) input
 

E x y	D0  D1  D2  D3
1 X X   0 0 0   0 0 1   0 1 0   0 1 1	1   1   1   1   0   1   1   1   1   0   1   1   1   1   0   1  1   1   1   0

3. Cascading decoders by using the E input (4 X 16 made by two 3 X 8)

4. Implementing combinational circuits using decoders:

• the decoder outputs generate the minterms
• add an OR gate to produce the sum
• Example: full adder S(x,y,z)=Sum(1,2,4,7); C(x,y,z)=Sum(3,5,6,7)

5. Multiplexers (decoder + 1 input for each AND + second level OR)
 

s1  s0	Output
0   0   0   1   1   0   1   1	I0   I1   I2  I3

6. Implementing Boolean functions with a multiplexer: assigning functional value to each input (each combination of select lines)

7. Cascading multiplexers (4-to-1 multiplexer made by three 2-to-1 multiplexers)

Designing an ALU

Lecture Notes:

1. The datapath and the ALU
2. ALU operations
• arithmetic and logic (add, sub, and, or)
• set on less than (slt)
3. Implementing subtraction:
• A-B = A+(-B)
• negation in two's complement: invert and add 1
4. Cascading 32 1-bit ALU's
5. Implementing subtraction - negation in two's complement: invert and add 1
1. Invert (multiplexer or XOR)
2. Add 1 - set the first carry to 1
6. Implementing slt: add Set and Less lines
7. Test for equality and completing the ALU

Using HDL to design combinational circuits

Lecture Notes:

1. Example: 2x4 decoder

module decoder_gl (A,B,E,D);
   input A,B,E;
   output [0:3]D;
   wire Anot,Bnot,Enot;
   not
      n1 (Anot,A),
      n2 (Bnot,B),
      n3 (Enot,E);
   nand
      n4 (D[0],Anot,Bnot,Enot),
      n5 (D[1],Anot,B,Enot),
      n6 (D[2],A,Bnot,Enot),
      n7 (D[3],A,B,Enot);
endmodule
 
2. Example: 4-bit adder

// Description of half adder (see Fig 4-5b)
module halfadder (S,C,x,y);
   input x,y;
   output S,C;
//Instantiate primitive gates
   xor (S,x,y);
   and (C,x,y);
endmodule

//Description of full adder (see Fig 4-8)
module fulladder (S,C,x,y,z);
   input x,y,z;
   output S,C;
   wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the halfadder
    halfadder HA1 (S1,D1,x,y),
              HA2 (S,D2,S1,z);
    or g1(C,D2,D1);
endmodule

//Description of 4-bit adder (see Fig 4-9)
module _4bit_adder (S,C4,A,B,C0);
   input [3:0] A,B;
   input C0;
   output [3:0] S;
   output C4;
   wire C1,C2,C3;  //Intermediate carries
//Instantiate the fulladder
   fulladder  FA0 (S[0],C1,A[0],B[0],C0),
              FA1 (S[1],C2,A[1],B[1],C1),
              FA2 (S[2],C3,A[2],B[2],C2),
              FA3 (S[3],C4,A[3],B[3],C3);
endmodule
 

1. Example: 2x4 decoder

// Dataflow description of a 2-to-4-line decoder
module decoder_df (A,B,E,D);
   input A,B,E;
   output [0:3] D;
   assign D[0] = ~(~A && ~B && ~E),
          D[1] = ~(~A && B && ~E),
          D[2] = ~(A && ~B && ~E),
          D[3] = ~(A && B && ~E);
endmodule
2. Example: 4-bit adder

// Dataflow description of 4-bit adder
module binary_adder (A,B,Cin,SUM,Cout);
   input [3:0] A,B;
   input Cin;
   output [3:0] SUM;
   output Cout;
   assign {Cout,SUM} = A + B + Cin;
endmodule

//Behavioral description of 2-to-1-line multiplexer
module mux2x1_bh(A,B,select,OUT);
   input A,B,select;
   output OUT;
   reg OUT;
   always @ (select or A or B)
         if (select == 1) OUT = A;
         else OUT = B;
endmodule

//Behavioral description of 4-to-1- line multiplexer
//Describes the function table of  Fig. 4-25(b).
module mux4x1_bh (i0,i1,i2,i3,select,y);
   input i0,i1,i2,i3;
   input [1:0] select;
   output y;
   reg y;
   always @ (i0 or i1 or i2 or i3 or select)
            case (select)
               2'b00: y = i0;
               2'b01: y = i1;
               2'b10: y = i2;
               2'b11: y = i3;
            endcase
endmodule

4. Simulation by using test bench

//Stimulus for mux2x1_df.
module testmux;
  reg TA,TB,TS;  //inputs for mux
  wire Y;       //output from mux
  mux2x1_df mx (TA,TB,TS,Y);  // instantiate mux
     initial
        begin
              TS = 1; TA = 0; TB = 1;
          #10 TA = 1; TB = 0;
          #10 TS = 0;
          #10 TA = 0; TB = 1;
        end
     initial
      $monitor("select = %b A = %b B = %b OUT = %b time = %0d",
               TS, TA, TB, Y, $time);
endmodule

//Dataflow description of 2-to-1-line multiplexer
//from Example 4-6
module mux2x1_df (A,B,select,OUT);
   input A,B,select;
   output OUT;
   assign OUT = select ? A : B;
endmodule

Read-only memory and PLA

Lecture Notes:

1. Implementing Boolean functions by using "programmable" decoders: minterms (decoder outputs) + OR gate (F). Array logic notation.
2. Read-only memory (ROM): (address space) X (word size), i.e. 2^n X m - sum of minterms
• Combinational logic implementation: decoder + fuses + OR gates (for each bit in the word), array logic notation for OR gates.
• Types of ROM: PROM, EPROM
3. Programmable logic array (PLA) - sum of products. Example: F1(A,B,C)=SUM(3,4,5,7), F2(A,B,C)=SUM(3,5,7)
• Simplify the functions for each output bit (using maps), F1=AB'+BC, F2=AC+BC
• Create a table with as many rows as the total number of products: 3 rows (AB', BC, AC)
• First column: product terms; second column: inputs; third column: outputs
• Draw the diagram using array logic notation
4. Example 1: MIPS CPU control
5. Example 2:
• F1(A,B,C)=SUM(0,1,2,4)
• F2(A,B,C)=SUM(0,5,6,7)
• Sum of product maps:
• F1 = A'B'+ A'C'+ B'C'
• F1'= AB + AC + BC
• F2 = AB + AC + A'B'C'
• F2'= A'C+ A'B + AB'C'
• Products: AB, AC, BC, A'B'C'
6. Example 3: PLA for BCD-to-seven-segment decoder (Problem 4.9).

Synchronous sequential logic: flip-flops

Lecture Notes:

1. Combinational and sequential logic
2. Synchronous and asynchronous logic:
• Synchronous: behavior is determined by the inputs signals at discrete instants of time (clock pulses), clocked sequential circuits.
• Asynchronous: behavior is determined by the signals at any instant of time and the order in which the inputs change.
3. Memory elements (binary storage): flip-flops
4. Basic flip-flops (operate with signal level).
• SR latch
• D latch: SR latch with control (enable input)
5. Edge-Triggered flip-flops:
• respond to clock pulse edges: positive and negative
• master-slave D flip-flop: samples the input during the high clock pusle level, changes the state (Q) at negative edge.
6. JK and T flip-flops
• JK flip-flop - changes the state at the clock pulse edge, implemented with a D flip-flop:  D=JQ'+K'Q
• T flip-flop - complements its state:
• implemented with JK flip-flop: T=J=K (T=1 changes the state).
• implemented with D flip-flop: D = TQ' + T'Q = T XOR Q
7. HDL implementations (T-flip-flop.vl)


module D_flip_flop(D,CLK,Q);
   input D,CLK;
   output Q;
   wire CLK1, Y;
   not  not1 (CLK1,CLK);
   D_latch D1(D,CLK, Y),
           D2(Y,CLK1,Q);
endmodule

module D_latch(D,C,Q);
   input D,C;
   output Q;
   wire x,y,D1,Q1;
   nand nand1 (x,D, C),
        nand2 (y,D1,C),
        nand3 (Q,x,Q1),
        nand4 (Q1,y,Q);
   not  not1  (D1,D);
endmodule

module test_D_flip_flop;
reg D,C;
wire Q;

D_flip_flop D1(D,C,Q);

  initial
     begin
           D=0; C=0;
       #10 D=0; C=1;
       #10 D=0; C=0;
       #10 D=1; C=0;
       #10 D=1; C=1;
       #10 D=0; C=1;
     end

  initial
     $monitor("%d %b %b %b",$time,D,C,Q);

endmodule

Designing a CPU

Lecture Notes:

1. Simple MIPS program
    
   li $t1, 7 # $t1 = 7
   li $t2, 5 # $t2 = 5 (4'b0101)
   sub $t3, $t1, $t2 # $t3 = 2 (7-5=2)
   li $t3, 10 # $t3 = 10 (4'b1010)
   or $t2, $t2, $t3 # $t2 = 15 (4'b1111)
   and $t3, $t2, $t3 # $t3 = 10 (4'b1010)
   slt $t2, $t3, $t2 # $t2 = 1
   add $t2, $t3, $t2 # $t2 = 11 (4'b1011=-5)
   add $t3, $t1, $t2 # $t3 = 2 (7+(-5)=2)
   slt $t1, $t2, $t3 # $t1 = 0
    
2. Instruction set architecture (instuction format)
3. Instruction register (D flip-flop register)
4. Register file (diagram)
5. CPU datapath and control (diagram)
6. HDL behavioral implementation (4-bitCPU.vl)

Analysis of clocked sequential circuits: finite state machines

Lecture Notes:

• RS flip-flop: Q(t+1)=SQ'(t)+R'Q(t)

S R	Q(t+1)
0 0   0 1   1 0   1 1	Q(t)   0   1  ?

• JK flip-flop: Q(t+1)=JQ'(t)+K'Q(t)

J K	Q(t+1)
0 0   0 1  1 0   1 1	Q(t)   0   1   Q'(t)

• D flip-flop: Q(t+1)=D

D	Q(t+1)
0   1	0   1

• T flip-flop: Q(t+1)=TQ'(t)+T'Q(t)

T	Q(t+1)
0  1	Q(t)  Q'(t)

• Logic diagram (D flip-flops)

DA = xA'B + xAB'
DB = xB'
y = AB


• State table: <present state> X <input> -> <next state>; <present state> -> <output>



Present state      A B	Input    x	Next state     A B	Output    y
0 0       0 0       0 1       0 1       1 0      1 0      1 1       1 1	0     1     0     1     0     1    0     1	0 0      0 1      0 0      1 0      0 0     1 1      0 0      0 0	0     0     0     0     0     0     1     1



• State diagram - finite state machines
• Mealy model: <present state> X <input> -> <output> (output may change during the pulse)
• Moore model: <present state> -> <output>

Designing clocked sequential circuits

Lecture Notes:

• D flip-flop
 

Q(t) Q(t+1)	D
0   0   0   1  1   0  1   1	0   1  0   1



•   T flip-flop
 

Q(t) Q(t+1)	T
0   0   0   1   1   0   1   1	0    1    1    0

Designing a sequential curcuit

Example: if x=1 count 0,1,2,3,0,1,2,3,... ; if x=0 no change; output y=1 if state=3 and x=1, else y=0.

1. Description of the circuit behavior: number of states, inputs, outputs, functionality.

2. State diagram (number of states -> number of flip-flops)

3. State table

 

Present state     A   B	Input    x	Next state    A   B	Output    y
0   0      0   0      0   1     0   1     1   0      1   0      1   1      1   1	0    1    0     1     0     1     0     1	0   0     0   1     0   1     1   0     1   0     1   1     1   1    0   0	0     0     0     0     0     0     0     1

 

Present state     A   B	Input    x	Next state    A   B	Flip-flop inputs    DA      DB
0   0      0   0      0   1      0   1     1   0     1   0      1   1      1   1	0     1     0     1    0     1     0     1	0   0     0   1     0   1     1   0    1   0     1   1     1   1     0   0	0       0    0       1     0       1     1       0     1       0     1       1     1       1     0       0

 

Present state     A   B	Input    x	Next state    A   B	Flip-flop inputs    TA      TB
0   0      0   0      0   1      0   1     1   0     1   0      1   1      1   1	0     1     0    1    0     1     0     1	0   0     0   1     0   1     1   0    1   0     1   1     1   1     0   0	0       0     0       1     0       0     1       1     0       0     0       1     0       0     1       1

7. Designing the combinational circuit (maps)

• D flip-flops:
• DA = xA'B + x'A + AB'
• DB = x'B + xB'
• T flip-flops:
• TA = xB
• TB = x

Register and counters

Lecture Notes:

1. Registers: a group of binary cells (flip-flops) suitable for storing binary information
• Gated latch: accepting inputs during the clock pulse (C=1). Example: a group of D flip flops (Fig.6-1)
• Loading registers
• Parallel loading: providing access to all inputs at a time.
• C controlled loading (C acts as an enable  signal)
• Load control input
• applied to C. Example: D flip-flops with their C input anded with the load control input (delay of C).
• applied to all data inputs. Register with D flip-flops: load control used to switch between previous state and input (Fig. 6-2).
• Building sequential circuits with registers: equivalent to the D flip-flop implementation of sequential circuits with load control=1.
• Shift registers: using edge triggered D flip-flops, serial input, serial output (Fig.6-3), shift control, serial transfer  (Fig.6-4)
• Serial addition (Fig. 6-5).
2. Counters
• Synchronous counters (C applied to all flip-flops): flip-flops + combinational logic (see "Designing clocked sequential circuits")
• Ripple counters: series of complementing flip-flops with the output of each flip-flop connected to the C input of the next one.
• Binary ripple counter: T flip-flops or D flip-flops  (Fig.6-8).
• BCD ripple counter: state diagram (Fig. 6-9), logic diagram (Fig.6-10).

Sample problems for Test 2 (Chapters 2 and 3)

• F = A'C' + ABC + AC' to a sum of two terms
• F = (x'y'+ z)'+ z + xy + wz to a sum of three variables
• F = A'B(D'+ C'D) + B(A + A'CD) to one variable

Problem 3: Transform F into canonical form as a sum of minterms using a map.

• F = (xy + z)(y + xz)
• F = (A'+ B)(B + C')

• F = (xy + z)(y + xz)
• F = (A'+ B)(B + C')

• F = (xy + z)(y + xz) (map)
• F = (A'+ B)(B + C')

F = xy'z + x'y'z + w'xy + wx'y + wxy

Problem 7: Using the map method simplify in sum of products the following functions. Show which map squares are covered by which term from the original function.

• F = x'z'+ y'z'+ yz'+ xy
• F = (A'+ B'+ D')(A + B'+ C')(A'+ B + D')(B + C'+ D')

• F = x'z'+ y'z'+ yz'+ xy
• F = (A'+ B'+ D')(A + B'+ C')(A'+ B + D')(B + C'+ D')

Review for Final Exam

• See Final Exam Review Questions in Blackboard
• Practice Problems
• Combinational circuits (Chapter 4). Problems: 4.9, 4.10, 4.11, 4.23, 4.25, 4.27, 4.28, 4.31, 4.32, 4.33
• ROM and PLA (Chapter 7). Problems 7.17, 7.18, 7.19, 7.20.
• Clocked sequential circuits (Chapter 5). Problems: 5.6 - 5.10, 5.16, 5.19, 5-20.

Project 1 (15 pts.)

Building and testing basic combinational circuits by using Verilog HDL

Project 2 (15 pts.)

Building a 4-bit ALU

Project 3 (15 pts.)

Building a 4-bit CPU