// Write port for the MIPS register file

module reg_file_write (wr,wd,regwrite,r1,r2,r3);

   input [1:0] wr;
   input [15:0] wd;
   input regwrite;
   output [15:0] r1, r2, r3;
   reg [15:0] r1, r2, r3;

   always@(wr,regwrite) 
         case (wr)
            2'b01: if (regwrite==1) r1 = wd; 
            2'b10: if (regwrite==1) r2 = wd; 
            2'b11: if (regwrite==1) r3 = wd; 
         endcase 

endmodule

module testing ();

 reg [1:0] wr;
 reg [15:0] wd;
 reg regwrite;
 wire [15:0] r1,r2,r3;

 reg_file_write regs (wr,wd,regwrite,r1,r2,r3);

 initial 
   begin  
         wd=12345;regwrite=0;wr=1;
     #10 wd=12345;regwrite=1;wr=1;
     #10 wd=12345;regwrite=0;wr=2;
     #10 wd=12345;regwrite=1;wr=2;
     #10 wd=12345;regwrite=0;wr=3;
     #10 wd=12345;regwrite=1;wr=3;
     #10 wd=0;    regwrite=0;wr=1;
     #10 wd=0;    regwrite=1;wr=1;
     #10 wd=0;    regwrite=0;wr=2;
     #10 wd=0;    regwrite=1;wr=2;
     #10 wd=0;    regwrite=0;wr=3;
     #10 wd=0;    regwrite=1;wr=3;

   end 

 initial
   $monitor ("wr=%d wd=%d regwrite=%d r1=%d r2=%d r3=%d",wr,wd,regwrite,r1,r2,r3);
 
endmodule 


/* Test results

C:\Verilog>iverilog -o t regfile.vl

C:\Verilog>vvp t
wr=1 wd=12345 regwrite=0 r1=    x r2=    x r3=    x
wr=1 wd=12345 regwrite=1 r1=12345 r2=    x r3=    x
wr=2 wd=12345 regwrite=0 r1=12345 r2=    x r3=    x
wr=2 wd=12345 regwrite=1 r1=12345 r2=12345 r3=    x
wr=3 wd=12345 regwrite=0 r1=12345 r2=12345 r3=    x
wr=3 wd=12345 regwrite=1 r1=12345 r2=12345 r3=12345
wr=1 wd=    0 regwrite=0 r1=12345 r2=12345 r3=12345
wr=1 wd=    0 regwrite=1 r1=    0 r2=12345 r3=12345
wr=2 wd=    0 regwrite=0 r1=    0 r2=12345 r3=12345
wr=2 wd=    0 regwrite=1 r1=    0 r2=    0 r3=12345
wr=3 wd=    0 regwrite=0 r1=    0 r2=    0 r3=12345
wr=3 wd=    0 regwrite=1 r1=    0 r2=    0 r3=    0

*/