// A template for the project version of MIPS (two stage control)

module CPU (clock, PC, IR, WD);

input clock; // the clock is an external input

// PC, IR, WD (Write Data) are available outside the module for testing
output [31:0] PC, IR;
reg [31:0] PC, IR;
output [31:0] WD;

reg [31:0] Memory [0:1023]; // Program and data memory
reg [1:0] state;            // Processor state

// Load a test program and data into memory
initial begin 

   // program
   Memory [0] = 32'h8C080040; // lw $8, 64($0)
   Memory [1] = 32'h01084820; // add $9, $8, $8

   // data starts at byte address 64
   Memory [16] = 32'd1;       // .word 1

end

// set the PC to 0 and start the control in state 0
initial begin PC = 0; state = 0; end

// The state machine - triggered on a rising clock

always @(posedge clock) begin

 case (state) //action depends on the state

  0: begin // Fetching phase
	IR <= Memory[PC>>2];
  // Replace PC + 4 with a wire from the output of the fetching ALU (instantiated before the always statement).
	PC <= PC + 4;
	state=1;
     end

  1: begin // Execute phase
 // Include the setting of execution control signals here and the datapath for execute before the always statement.
	state = 0;
    end
 endcase

end

endmodule

//--------------------------------------------------------------------
//  Test module

module test_mips ();

reg clock;
wire [31:0] PC, IR, WD;

CPU cpu1(clock, PC, IR, WD);

always begin #1 clock = ~clock; end

initial begin
  $monitor ("%d %d PC=%2d IR=%h WD=%2d", $time,clock,PC,IR,WD);
  clock = 0;
  #10 $finish;
end
endmodule

//--------------------------------------------------------------------
/* Compile and execute

C:\Verilog\bin>iverilog -o t mips2.vl

C:\Verilog\bin>vvp t
                   0 0 PC= 0 IR=xxxxxxxx WD= z
                   1 1 PC= 4 IR=8c080040 WD= z
                   2 0 PC= 4 IR=8c080040 WD= z
                   3 1 PC= 4 IR=8c080040 WD= z
                   4 0 PC= 4 IR=8c080040 WD= z
                   5 1 PC= 8 IR=01084820 WD= z
                   6 0 PC= 8 IR=01084820 WD= z
                   7 1 PC= 8 IR=01084820 WD= z
                   8 0 PC= 8 IR=01084820 WD= z
                   9 1 PC=12 IR=xxxxxxxx WD= z
*/