// 4-bit MIPS ALU in Verilog

module ALU (op,a,b,result,zero);
   input [3:0] a;
   input [3:0] b;
   input [2:0] op;
   output [3:0] result;
   output zero;
   wire c1,c2,c3,c4;
	
   ALU1   alu0 (a[0],b[0],op[2],op[1:0],set,op[2],c1,result[0]);
   ALU1   alu1 (a[1],b[1],op[2],op[1:0],0,  c1,   c2,result[1]);
   ALU1   alu2 (a[2],b[2],op[2],op[1:0],0,  c2,   c3,result[2]);
   ALUmsb alu3 (a[3],b[3],op[2],op[1:0],0,  c3,   c4,result[3],set);

   or or1(or01, result[0],result[1]);
   or or2(or23, result[2],result[3]);
   nor nor1(zero,or01,or23);

endmodule


// 1-bit ALU for bits 0-2

module ALU1 (a,b,binvert,op,less,carryin,carryout,result);
   input a,b,less,carryin,binvert;
   input [1:0] op;
   output carryout,result;
   wire sum, a_and_b, a_or_b, b_inv;
	
   not not1(b_inv, b);
   mux2x1 mux1(b,b_inv,binvert,b1);
   and and1(a_and_b, a, b);
   or or1(a_or_b, a, b);
   fulladder adder1(sum,carryout,a,b1,carryin);
   mux4x1 mux2(a_and_b,a_or_b,sum,less,op[1:0],result); 

endmodule


// 1-bit ALU for the most significant bit

module ALUmsb (a,b,binvert,op,less,carryin,carryout,result,sum);
   input a,b,less,carryin,binvert;
   input [1:0] op;
   output carryout,result,sum;
   wire sum, a_and_b, a_or_b, b_inv;
	
   not not1(b_inv, b);
   mux2x1 mux1(b,b_inv,binvert,b1);
   and and1(a_and_b, a, b);
   or or1(a_or_b, a, b);
   fulladder adder1(sum,carryout,a,b1,carryin);
   mux4x1 mux2(a_and_b,a_or_b,sum,less,op[1:0],result); 

endmodule


module halfadder (S,C,x,y); 
   input x,y; 
   output S,C; 

   xor (S,x,y); 
   and (C,x,y); 
endmodule 


module fulladder (S,C,x,y,z); 
   input x,y,z; 
   output S,C; 
   wire S1,D1,D2;

   halfadder HA1 (S1,D1,x,y), 
             HA2 (S,D2,S1,z); 
   or g1(C,D2,D1); 
endmodule 


module mux2x1(A,B,select,OUT); 
   input A,B,select; 
   output OUT; 
   reg OUT; 
   always @ (select or A or B) 
         if (select == 0) OUT = A; 
         else OUT = B; 
endmodule 

module mux4x1(i0,i1,i2,i3,select,y); 
   input i0,i1,i2,i3; 
   input [1:0] select; 
   output y; 
   reg y; 
   always @ (i0 or i1 or i2 or i3 or select) 
            case (select) 
               2'b00: y = i0; 
               2'b01: y = i1; 
               2'b10: y = i2; 
               2'b11: y = i3; 
            endcase 
endmodule 


// Test Module 

module testALU;
   reg [3:0] a;
   reg [3:0] b;
   reg [2:0] op;
   wire [3:0] result;
   wire zero;
	
   ALU alu (op,a,b,result,zero);
	
   initial
      begin

	    op = 3'b000; a = 4'b0111; b = 4'b0001;  // AND
	#10 op = 3'b001; a = 4'b0101; b = 4'b0010;  // OR

	#10 op = 3'b010; a = 4'b0101; b = 4'b0001;  // ADD
	#10 op = 3'b010; a = 4'b0111; b = 4'b0001;  // ADD
	#10 op = 3'b110; a = 4'b0101; b = 4'b0001;  // SUB
	#10 op = 3'b110; a = 4'b1111; b = 4'b0001;  // SUB
	#10 op = 3'b111; a = 4'b0101; b = 4'b0001;  // SLT
	#10 op = 3'b111; a = 4'b1110; b = 4'b1111;  // SLT

      end

   initial
    $monitor ("op = %b a = %b b = %b result = %b zero = %b",op,a,b,result,zero);

endmodule


/* Test Results

C:\Verilog>iverilog -o t ALU4.vl

C:\Verilog>vvp t
op = 000 a = 0111 b = 0001 result = 0001 zero = 0
op = 001 a = 0101 b = 0010 result = 0111 zero = 0
op = 010 a = 0101 b = 0001 result = 0110 zero = 0
op = 010 a = 0111 b = 0001 result = 1000 zero = 0
op = 110 a = 0101 b = 0001 result = 0100 zero = 0
op = 110 a = 1111 b = 0001 result = 1110 zero = 0
op = 111 a = 0101 b = 0001 result = 0000 zero = 1
op = 111 a = 1110 b = 1111 result = 0001 zero = 0

*/