• May 7, 4:30 - 6:30 pm: Semester project presentation
• May 7-12: Final Exam to be taken online
• May 12: Semester Project Final Report due

CS385 – Computer Architecture

Spring-2012

Catalog description: The architecture of the computer is explored by studying its various levels: physical level, operating-system level, conventional machine level and higher levels. An introduction to microprogramming and computer networking is provided.

Course Prerequisites: CS 354

Prerequisites by topic

• Basic skills in software design and programming
• Assembly language programming and basics of computer organization
• Digital systems design
• Boolean algebra and discrete mathematics

The course provides a comprehensive coverage of computer architecture. It discusses the main components of the computer and the basic principles of its operation. It demonstrates the relationship between the software and the hardware and focuses on the foundational concepts that are the basis for current computer design. The course is based on the MIPS processor, a simple clean RISC processor whose architecture is easy to learn and understand. The major topics covered in the course are the following:

1. MIPS instruction set
2. Computer arithmetic and ALU design
3. Datapath and control
4. Using Hardware Description Language to design and simulate the CPU
5. Pipelining
6. Memory hierarchy, caches and virtual memory
7. Interfacing CPU and peripherals, buses
8. Multiprocessors, networks of multiprocessors, parallel programming
9. Performance issues

Upon successful completion of the course the student will be able to

1. Understand the fundamentals of different instruction set architectures and their relationship to the CPU design.
2. Understand the principles and the implementation of computer arithmetic.
3. Understand the operation of modern CPUs including pipelining, memory systems and busses.
4. Understand the principles of operation of multiprocessor systems.
5. Design and emulate a single cycle or pipelined CPU by given specifications using HDL.
6. Write simple parallel programs.
7. Work in teams to design and implement CPUs.
8. Write reports and make presentations about their computer architecture projects.

• Objective 1. Graduates will have a broad understanding of the fundamental theories, concepts, and applications of computer science.
• Outcome a: An ability to apply knowledge of computing and mathematics appropriate to the discipline
• Outcome b: An ability to analyze a problem, and identify and define the computing requirements appropriate to its solution
• Outcome c: An ability to design, implement, and evaluate a computer-based system, process, component, or program to meet desired needs.
• Objective 2. Graduates will be prepared for careers in computer science and information technology.
• Outcome i: An ability to use current techniques, skills, and tools necessary for computing practice.
• Outcome j: An ability to apply mathematical foundations, algorithmic principles, and computer science theory in the modeling and design of computer-based systems in a way that demonstrates comprehension of the tradeoffs involved in design choices.
• Objective 3. Graduates will communicate effectively, both orally and in writing.
• Outcome (d): An ability to function effectively on teams to accomplish a common goal.
• Outcome (f): An ability to communicate effectively.

Required software:

1. Icarus Verilog: HDL compiler and simulator, available on the Patterson and Hennessy's book CD or at http://bleyer.org/icarus/. Note about installation: don't use folder names that include spaces (like Program Files). Read book sections B.4 and 5.8 for using HDL.
2. Other simulators that may be used for drawing logic diagrams and experimenting with small circuirs (note that the semester project should be done with Verilog):
• Digital Works 2.0 (freeware, http://www.cs.ccsu.edu/~markov/ccsu_courses/digwork.zip)
• Digital Works 3.04 (fully functional demo version, http://www.electronics-lab.com/downloads/schematic/002/index.html)
3. SPIM simulator: A free software simulator for running MIPS R2000 assembly language programs available for Unix, DOS, and Windows.

Class Participation: Active participation in class is expected of all students. Regular attendance is also expected. If you must miss a class, try to inform the instructor of this in advance.In case of missed classes and work due to plausible reasons (such as illness or accidents) limitted assistance will be offered. Unexcused absences will result in the student being totally responsible for the make-up process.

Honesty policy: The CCSU honor code for Academic Integrity is in effect in this class. It is expected that all students will conduct themselves in an honest manner and NEVER claim work which is not their own. Violating this policy will result in a substantial grade penalty, and may lead to expulsion from the University. You may find it online at http://web.ccsu.edu/academicintegrity/UndergradAcadMisconductPolicy.htm. Please read it carefully.

Grading: Grading will be based on one programming assignment (10%), a midterm test (20%, taken online), a final exam (25%, taken online) and a semester project (45%, including progress reports, the final documentation, and the presentation). The letter grades will be calculated according to the following table:
 

A	A-	B+	B	B-	C+	C	C-	D+	D	D-	F
95-100	90-94	87-89	84-86	80-83	77-79	74-76	70-73	67-69	64-66	60-63	0-59

Unexcused late submission policy: Submissions made more than two days after the due date will be graded one letter grade down. Submissions made more than a week late will receive two letter grades down. No submissions will be accepted more than two weeks after the due date.

Tentative schedule of classes and assignments

1. January 18: Introduction: Computer Architecture = Instruction Set Architecture + Machine Organization
2. January 23: MIPS Instructions: arithmetic, registers, memory, fecth&execute cycle
3. January 25: MIPS Instructions: control and addressing modes
4. January 30: Computer arithmetic and ALU design: representing numbers, arithmetic and logic operations
5. February 1: ALU design: full adder, slt operation, HDL design, carry lookahead
6. February 6: Assignment 1 due (10 pts.)
7. February 6: ALU design: multiplication, representing floating point numbers
8. February 8: The Processor: Building a datapath
9. February 13: The Processor: Control (single cycle approach)
10. February 15: Using a Hardware Description Language to Design and Simulate the MIPS processor
11. February 22: Turing machines
12. February 27: Introduction to pipelining
13. February 29: Progress Report #1 due (10 pts.): A simpilfied single-cycle datapath capable of executing the addi instruction and all R-typeinstructions. See Semester Project for details.
14. March 5: Solving pipeline hazards
15. March 7: Implementing pipeline datapath and control
16. March 12: Implementing data and branch hazards control
17. March 14: Review of Datapath, Control and Pipelining, HDL implementation
18. March 14-18: Midterm Test (20 pts.) to be taken online in BB Vista
19. March 28: Progress Report #2 due (10 pts.): Complete single-cycle datapath. See Semester Project for details.
20. March 26: Memory hierarchy
21. April 2: The Basics of caches
22. April 4: Improving cache performance
23. April 9: Virtual Memory basics
24. April 11: Virtual Memory optimization
25. April 16: Progress Report #3 due (10 pts.): 3-stage pipelined datapath for addi and R-type instructions. See Semester Project for details.
26. April 16: A general framework of memory hierarchies
27. April 16: Interfacing Processors and Peripherals - Buses
28. April 23: Interfacing I/O devices to Memory, CPU and OS
29. April 25: Multiprocessors
30. April 30, May 2: Networks of muiltiprocessors
31. May 12: Semester Project Final Report due (10 pts.)
32. May 7-12: Final Exam (25 pts.) to be taken online
33. May 7, 4:30 - 6:30 pm: Semester project presentation (5 pts.)

CS385 – Computer Architecture, Lecture 1

Lecture Notes

1. Levels of Abstraction
2. Computer Architecture = Instruction Set Architecture + Machine Organization
3. Instruction Set – The Software Hardware Interface
4. Levels of Computer Architecture in More Depth
• Software:
• Application
• Operating System
• Firmware
• Instruction Set Architecture:
• Organization of Programmable Storage
• Data type and Structures: encodings and machine representation
• Instruction set
• Instruction Formats
• Addressing Modes and Accessing Data and Instructions
• Exception Handling
• Hardware:
• Instruction Set Processing
• I/O System
• Digital Design
• Circuit Design
• Layout
5. Basic Components of a Computer
• Processor: Datapath and Control
• Memory
• I/O
6. Computer Organization
• Capabilities and Performance of the Basic Functional Units
• The Way These Units are Interconnected
• Information Flow between components
• Information Flow Control
7. Performance (Lecture slides (PDF)
• Measuring and improving computer performance:
• Program execution time
• CPU time: user CPU time and system CPU time
• Power
• Evaluating computer systems:
• Relative performance
• Workload
• Benchmarks
• Multiprocessors and Parallelism
• Single instruction stream, single data stream (SISD)
• Single instruction stream, multiple data streams (SIMD)
• Multiple instruction streams, single data stream (MISD)
• Multiple instruction streams, multiple data streams (MIMD)

CS385 – Computer Architecture, Lecture 2

Lecture Notes

1. Design goal: maximize performance and minimize cost. Primitive (low level) and very restrictive instructions (fixed number and type of operands).
2. Design principles:
• Simplicity favors regularity (uniform instruction format)
• Smaller is faster (only 32 registers)
• Good design demands a compromise (I-type instructions)
3. MIPS arithmetic: 3 operands, fixed order, registers only.
4. Using only registers: R-type instructions.
5. Registers: 32-bits long, conventions.
6. Memory organization: words and byte addressing.
7. Data transfer (load and store) instructions. Example: accessing array elements.
8. Translating C code into MIPS instructions – the swap example.
9. Machine Language: instruction format, I-type (Immediate) format for data transfer
10. Stored program concept: programs in memory, fetch?execute cycle
• Von Neumann Architecture
• CPU, Memory System, I/O system
• Stored program concept: programs in memory, fetch?execute cycle
• Instructions are executed sequentially
• Turing machines
• Alan Turing web page
• Turing machines
• A Turing Machine Applet
• Non-Von Neumann Architecture:
• Various parallel and multiprocessor architectures
• In broader sense: NN, GA etc.
• The Modern History of Computing
• John von Neumann

CS385 – Computer Architecture, Lecture 3

Lecture Notes

1. Implementing the C code for if in MIPS: conditional branch.
2. Implementing the C code for if–else in MIPS: unconditional branch
3. Simple for loop
4. Check for less-than: building a pseudoinstuction for branch if less-than.
5. Addressing in branch instructions: PC-relative and pseudodirect.
6. Constants: use of immediate addressing (constants as operands – addi, slti, andi, ori)).
7. 32-bit constants – manipulate upper 2 bytes separately (load upper immediate)
8. Summary of MIPS addressing: register (add), immediate (addi), base or displacement (lw), PC-relative (bne), pseudodirect (j).
9. Alternative approaches: IA-32

CS385 – Computer Architecture, Lecture 4

Lecture Notes

1. Representing numbers: sign bit, one's complement, two's complement.
2. Arithmetic: addition, subtraction, detecting overflow.
3. Logical operations: shift, and, or.
4. Basic ALU building components: and-gate, or-gate, inverter, multiplexor.
5. ALU for logical operations.
6. ALU for add, and, or.
7. Supporting subtraction

Tutorials and practice quizzes on two’s complement numbers:

• http://chortle.ccsu.edu/AssemblyTutorial/Chapter-08/ass08_1.html (tutorial)
• http://chortle.ccsu.edu/AssemblyTutorial/Chapter-08/ass08quiz.html (quiz)

CS385 – Computer Architecture, Lecture 5

1. Implementation of a full adder:
• Carry out logic
• Result logic: using 'and', 'or' and inverter and using xor-gate.
2. Supporting set on less-than (slt).
3. Test for equality (needed for branching)
4. Designing the ALU in Verilog
5. Carry Lookahead

CS385 – Computer Architecture, Lecture 6

Lecture Notes

1. Implementing multiplication:
• Using 64-bit adder;
• Using 32-bit adder for the upper 32-bit of the product;
• Avoiding the use of the multiplier register.
2. Floating point numbers
• Scientific notation: (-1)^sign * significand * 2^exponent
• Range and precision (overflow and underflow).
• IEEE 754 floating point standard - allows integer comparison:
• normalized representation
• implicit leading 1
• exponent is biased: exponent in [0..0 (most negative), 1..1 (most positive)]
• bits of the significand represent the fraction between 0 and 1.
• (-1)^S * (1 + s1*2^-1 + s2*2^-2 + ...) * 2^(exponent-bias)
• Problems with floating point arithmetic

• http://chortle.ccsu.edu/AssemblyTutorial/Chapter-30/ass30_1.html (tutorial)
• http://chortle.ccsu.edu/AssemblyTutorial/Chapter-30/ass30quiz.html (quiz)

CS385 – Computer Architecture, Lecture 7

Lecture Notes

1. Abstract level implementation:
• Instruction memory
• Program counter
• Register file
• ALU
• Data memory
2. Basic building elements
• Combinational logic
• State elements: D-lathes and D flip-flops
• Clocking methodology: edge triggered
3. Fetching instructions and incrementing the program counter
4. Register file and execution of R-type instructions
5. Datapath for lw and sw instructions (add data memory and sign extend)
6. Datapath for branch instructions

• http://www.it.jcu.edu.au/Subjects/cp2005/resources/animation/wk6animations.ppt
• https://www.cs.tcd.ie/Jeremy.Jones/vivio/dlx/showanim.php?name=Tutorial01

CS385 – Computer Architecture, Lecture 8

Lecture Notes

1. ALU control: mapping the opcode and function bits to the ALU control inputs
2. Designing the main control unit
3. Operation of the Datapath (single-cycle implementation):
• R-type instructions
• Load (store) word
• Branching instructions
4. Problems of the single-cycle implementation

CS385 – Computer Architecture, Lecture 11

1. Behavior model of MIPS - single cycle implementation: mips-simple.vl
2. Project version (progress report #2). Changes needed:
• Adjust the word size (ALU, registers, memory etc.) to 16 bit
• Modify datapath control to reflect the instruction set architecture
• Add addi and bne instructions
• Write a complete program for testing and test the CPU

• Implement the addi instruction by:
• adding a new row to the single cycle main control table
• modifying the HDL code (mips-r-type+addi.vl, test-r-addi.asm)

Turing machines

1. Turing machines
2. Alan Turing web page
3. A Turing Machine Applet
4. A real, physical Turing machine, with video

CS385 – Computer Architecture, Lecture 13

Lecture Notes

1. Pipelining by analogy (laundry example):
• Pipelining helps throughput of the entire workload
• Multiple tasks operating simultaneously and using different resources
• Potential speedup = number of pipe stages
• The pipeline rate is limited by the slowest stage
• Unbalanced lengths of pipe stages reduces the speedup
• The time to "fill" the pipeline and the time "drain" it reduces the speedup
• Stall for dependencies
2. Five stages of the load MIPS instruction
3. The pipelined datapath
4. Single cycle, multiple cycle vs. pipeline
5. Advantages of pipelined execution
6. Problems with pipelining (pipeline hazards)
• Structural hazards
• Data hazards
• Control hazards

CS385 – Computer Architecture, Lecture 14

Lecture Notes

1. Structural hazards: single memory
2. Control hazards:
• Stall: wait until decision is clear
• Predict: fixed prediction (e.g. fail), dynamic prediction (based on history)
• Delayed brach (software solution):
add $4, $5, $6            beq $1, $2, $40
beq $1, $2, 40     ==>    add $4, $5, $6
lw $3, 300($0)            lw $3, 300($0)
3. Data hazards (dependecies backwards in time):
• Forwarding (bypassing)
• Reordering code
lw $t0, 0($t1)               lw $t0, 0($t1)
lw $t2, 4($t1)      ==>      lw $t2, 4($t1)
sw $t2, 0($t1)               sw $t0, 4($t1)
sw $t0, 4($t1)               sw $t2, 0($t1)
4. Designing a pipelined processor

CS385 – Computer Architecture, Lecture 15

Lecture Notes

1. Splitting datapath into stages: using registers to store parts of the instruction
2. Transferring data forward and backward between the stages: lw example
3. Corrected datapath: storing rd for the write back stage.
4. Graphically representing pipelines: multiple-clock-cycle vs. single-clock-cycle diagram
5. Pipeline control:
• IF: no control signals to store for later stages (they are always asserted).
• ID: no control signals to store for later stages (they are always asserted).
• EX: set RegDst, ALUOp, ALUSrc
• MEM: set Branch, MemRead, MemWrite
• WB: set MemtoReg, RegWrite
6. Datapath with control
7. Example: running this code through the pipeline in 9 cycles.

lw   $10, 20($1)
sub  $11, $2, $3
and  $12, $4, $5
or   $13, $6, $7,
add  $14, $8, $9

Demo: https://www.cs.tcd.ie/Jeremy.Jones/vivio/dlx/showanim.php?name=Tutorial09

CS385 – Computer Architecture, Lecture 16

Lecture Notes

1. Detecting data dependencies
• EX/MEM.Rd = ID/EX.Rs

EX/MEM.Rd = ID/EX.Rt
• MEM/WB.Rd = ID/EX.Rs

MEM/WB.Rd = ID/EX.Rt
2. Forwarding
• if (EX/MEM.RegWrite and EX/MEM.Rd = ID/EX.Rs)ForwardA = 10

if (EX/MEM.RegWrite and EX/MEM.Rd = ID/EX.Rt)ForwardB = 10
• if (MEM/WB.RegWrite and MEM/WB.Rd = ID/EX.Rs)ForwardA = 01

if (MEM/WB.RegWrite and MEM/WB.Rd = ID/EX.Rt)ForwardB = 01
3. Data hazards and stalls

If (ID/EX.MemRead and
    (ID/EX.Rt = IF/ID.Rs or
     ID/EX.Rt = IF/ID.Rt))
   stall the pipeline
4. Branch hazards
• Reducing the delay of branches - move up the address calculation (move the adder) and the branch decision (add XOR and AND gates)
• Assuming the branch will not be taken
• Flashing instructions in IF, ID, and EX stages, if the branch is taken
5. Advanced pipelining
• Superpipelining
• Superscalar
• Dynamic scheduling

CS385 – Computer Architecture, Lecture 17

Lecture slides (PDF)

Lecture Notes

Datapath

1. Abstract level implementation:
• Instruction memory
• Program counter
• Register file
• ALU
• Data memory
2. Basic building elements
• Combinational logic
• State elements: D-lathes and D flip-flops
• Clocking methodology: edge triggered
3. Basic operations
• Instructions fetch
• Accessing register file and execution of R-type instructions
• Datapath for lw and sw instructions (add data memory and sign extend)
• Datapath for branch instructions

Control

1. ALU control: mapping the opcode and function bits to the ALU control inputs
2. Designing the main control unit
3. Operation of the Datapath (single-cycle implementation):
• R-type instructions
• Load (store) word
• Branching instructions
4. Problems of the single-cycle implementation
5. Multicycle Approach to Processor Control
6. Basic principles of the Multicycle Approach to Processor Control
• Breaking up instruction into steps
• Reusing functional units in different steps
• Storing intermediate results
• Need for controlling the sequence of steps
7. Execution steps:
• Instruction fetch
• Instruction decoding and register fetch
• Instruction dependent (memory reference, R-type execution or branch)
• R-type completion or memory access
• Memory read completion
8. Finite state machine control
9. Microprogramming

Pipelining

1. Basic principles of pipelining
• Pipelining helps throughput of the entire workload
• Multiple tasks operating simultaneously and using different resources
• Potential speedup = number of pipe stages
• The pipeline rate is limited by the slowest stage
• Unbalanced lengths of pipe stages reduces the speedup
• The time to "fill" the pipeline and the time "drain" it reduces the speedup
• Stall for dependencies
2. MIPS pipelining: the five stages of the lw instruction
3. Problems with pipelining:
• Structural hazards
• Data hazards
• Control hazards
4. Designing a pipelined processor
5. Transferring data forward and backward between the stages
6. Pipeline control
7. Implementing data and branch hazard control
• Detecting data dependencies
• Forwarding
• Data hazards and stalls
• Branch hazards
8. Advanced pipelining

Demo:

• http://www.it.jcu.edu.au/Subjects/cp2005/resources/animation/wk6animations.ppt
• https://www.cs.tcd.ie/Jeremy.Jones/vivio/dlx/showanim.php?name=Tutorial01
• https://www.cs.tcd.ie/Jeremy.Jones/vivio/dlx/showanim.php?name=Tutorial09

CS385 – Computer Architecture, Lecture 18

Lecture Notes

1. Memory technologies and trends
2. Impact on performance
3. The need of hierarchical memory organization
4. The principle of locality
5. Memory hierarchy terminology
6. Basics of RAM implementation
• SRAM:  D-latches, three-state buffers, address decoders, two level addressing
• DRAM:  DRAM cell, refreshing
• Error detection and correction

CS385 – Computer Architecture, Lecture 19

Lecture Notes

1. Direct-mapped cache
2. Accessing a cache
• Cash index
• Tag
• Valid bit
3. Writing to the cache (write-through and write-back schemes)
4. Handling cache misses
• Read miss: load the word from memory
• Write miss: write both to the cache and to the memory (using write buffer)
5. Example: DECStation 3100 cache
6. Spatial locality caches: keeping consistency on write
7. Main memory organization

CS385 – Computer Architecture, Lecture 20

Lecture Notes

1. Measuring cache performance
• Stall clock cycles = Instructions * Miss rate * Miss penalty
• Example 1 (reducing CPI):
• 2% - instruction miss; 4% - data miss; 36% - lw/sw; 40 cyc - miss penalty.
• 2 CPI => CPI_stall = 3.36, i.e. perfect cache is 1.68 times faster.
• 1 CPI => CPI_stall = 2.36, i.e. perfect cache is 2.36 times faster.
• Example 2: doubling clock rate => 80 cyc - miss penalty, CPI_stall = 4.75, Performance: 3.36/(4.75/2) = 1.41 faster with stalls, 2 times faster without stalls.
• Conclusion: cache penalties increase as the machine becomes faster
2. Flexible placement of blocks in the cache
• Direct mapped: Cache index = (Block address) modulo (Cache size); no search; small tag.
• Set associative: Cache index = (Block address) modulo (Number of sets in cache); search the set; larger tag.
• Fully associative: Cache index is not determined; search the whole cache; tag = address.
3. Locating a block in the cache: N-way cache requires N comparators and N-way multiplexor
4. Choosing which block to replace: least recently used
5. Multilevel caches

• Write a sequence of memory references for which:
• the direct mapped cache performs better than the 2-way associative cache;
• the 2-way associative cache performs better than the fully associative cache.
• Exercises 5.3, 5.4 (pages 550, 551).

CS385 – Computer Architecture, Lecture 21

Lecture Notes

1. The need of VM
• Many programs (processes) can use a single memory
• Use a memory exceeding the size of the main memory
2. VM organization and terminology: virtual address, physical address, page, page offset, page fault, memory mapping (translation).
3. Design decisions motivated by the very high cost of page faults:
• Large pages (4K-64K)
• Reducing page fault penalties: fully associative VM
• Software management of page faults
• Write-back instead of write-through
4. Addressing pages:
• Page table, page table register
• Processes (active, inactive) and page tables
• Page faults
• Replacing pages: LRU, reference (use) bit
• Write-back scheme (dirty bit)

CS385 – Computer Architecture, Lecture 22

Lecture Notes

1. Optimizing address translation - Translation Lookaside Buffer (TLB):
• TLB miss
• Page fault
• TLB associativity
2. MIPS R2000 (DECStation 3100) TLB
3. Overall operation of a memory hierarchy
4. Memory protection with VM
5. Using exceptions for handling TLB misses and pages faults: using EPC and Cause registers
6. Summary of VM

CS385 – Computer Architecture, Lecture 23

Lecture Notes

1. Associativity schemes
2. Placing blocks
3. Miss rates and cache sizes
4. Finding blocks
5. Why do we use full associativity and a separate lookup table (page table) in VM
6. Choosing a block to replace
7. Writing blocks
8. The sources of misses
9. The challenge: reducing the miss rate has a negative effect on the overall performance
10. Pentium Pro and PowerPC 604

Exercises

CS385 – Computer Architecture, Lecture 24

Lecture Notes

1. Buses: lines, transactions, types
2. Synchronous and asynchronous buses
3. Handshaking protocol
4. Bus access: master and slave
5. Bus arbitration schemes
6. Bus standards

CS385 – Computer Architecture, Lecture 25

Lecture Notes

1. The role of the operating system in interfacing I/O devices to Memory
2. Controlling the I/O devices
• Memory mapped I/O
• Special I/O instructions
3. Communicating with the processor
• Polling
• Interrupt-driven I/O
4. Direct memory access (DMA)
5. DMA and the memory system
6. Designing an I/O system: latency and bandwidth constraints.

CS385 – Computer Architecture, Lecture 26

Lecture Notes

1. Basic approaches to sharing data and types of connectivity
2. Programming multiprocessors
3. Multiprocessors connected by a single bus
4. A parallel program
5. Multiprocessor cache coherency
6. Implementing a multiprocessor cache coherency protocol
7. Synchronization using coherency

CS385 – Computer Architecture, Lecture 27

Lecture Notes

1. Shared memory vs. multiple private memories
2. Centralized memory vs. distributed memory
3. Parallel programming by message passing
4. Distributed memory communication
5. Memory allocation
6. Clusters and network topology
7. Modern clusters:
• The Beowulf Project
• AppleSeed Project
• BOINC
• SETI@home
• Folding@home
• List of distributed computing projects from Wikipedia

CS385 Assignment 1: Assembly Programming in MIPS (maximum grade 10 points)

The program must include:

1. At least one instruction from each instruction type: R-type arithmetic, I-type arithmetic, Memory transfer and Branch.
2. Input and Output through system calls.
3. Detailed comments explaining the type, format and the meaning of each instruction including the compiler directives. If you use a pseudo instruction, there must be an explanation how it translates into real MIPS instructions and the latter must be commented too.

Documentation and submission: Submit the source of the program (plain text file) as an attachment through Blackboard Vista Courses > CS-385 > Assignment 1. 

CS385 Semester Project: Building a mini MIPS machine (maximum grade 45 points including the presentation)

Description: Design a simplified version of a MIPS machine and write Verilog programs that describe its structure and simulate its functioning. Use structural (gate level) modeling for all components unless otherwise specified. The machine should include the following components:

1. General purpose registers (register file): 4 registers, 16-bit long, numbered 0 - 3. Register $0 must contain 0 (read-only). Implemented by D flip-flops with gate-level modeling.
2. Other registers: 16-bit program counter, pipeline registers. Implemented by reg data type in Verilog.
3. Istruction Memory. Word size: 16 bits, word addressed, size: 1024 bytes. Implemented by reg data type in Verilog.
4. Data Memory. Word size: 16 bits, byte addressed, size: 1024 bytes. Implemented by reg data type in Verilog.
5. Data Cache (optional): direct mapped, write-through, 16-bit block size, size: 8 blocks. Any kind of Verilog model accepted.
6. ALU: 16-bit data, 3-bit control (and, or, add, sub, slt).
7. Control unit: may be implemented by behavioral modeling.
8. Other components necessary to connect the main components: multiplexes and decoders implemented by gate-level modeling.

Instruction formats:

R-format (add, sub, and, or, slt)

op	rs	rt	rd	unused
4	2	2	2	6

I-format (addi, lw, sw, beq, bne)

op	rs	rt	address / value
4	2	2	8

Restrictions:

1. Use structural (gate level) modeling for all components except for the program counter, memories, and pipeline registers.
2. Implement a pipelined datapath and control.

Testing: To test the MIPS machine write a simple program that includes arithmetic (add, sub), data transfer (lw, sw) and branch (beq or bne) instructions. Use the addi instruction to introduce numeric constants in your program. For example, this may be a program that sums up 5 consecutive memory words by using a loop and stores the result in a register. Include in your report:

1. The assembly source of the test program with comments explaining the algortihm
2. The machine code (the contents of the memory)
3. Simulation results obtained by running the Verilog program. To monitor the execution of the test program for each instruction display the value at the write data input of the register file.

1. The names of the team members  and the tasks that each one accomplished.
2. A diagram showing the design of the processor with labels for all components and signals corresponding exactly to the mudules, input/outputs and wire names used in the Verilog code.
3. The Verilog source code including detailed comment for each module defined or used.
4. Test result showing correct functioning of the components obtained by running a test program. The source and the machine language translation of the program must be included too.

1. Due on February 29: A simpilfied single-cycle datapath capable of executing the addi instruction and all R-type instructions. Major components: Instruction memory, ALU, and Register File. Use template files: ALU4.vl (extend it to 16 bit) and regfile.vl (change the D flip-flops with 16-bit registers and redesign mux4x1 using gate-level modeling and extend it to 16-bit data). See the behavioral implementation mips-r-type+addi.vl. Include in the report: Verilog sources and test results. For testing use the test program test-r-addi.asm and adjust it to the 16-bit version of MIPS following the requirements given in section "Testing".
2. Due on March 28: Complete single-cycle datapath. Implement all instructions and run a complete test program as explained in section "Testing". See the behavioral model of MIPS mips-simple.vl for the implementation of the data memory and branching logic. Use the test program from mips-simple.vl extended with a bne instruction. Include in the report: A top-level diagram of the datapath, Verilog source files and test results
3. Due on April 16: 3-stage pipelined datapath for addi and R-type instructions.Write a test program that includes all R-type instructions and addi, and run it through the pipeline. Use the 3-stage behavioural model mips-pipe3.vl and make the necessary changes. Include in the report: A top-level diagram of the datapath, Verilog source files and test results.
4. May 7, 4:30 - 6:30 pm: Semester project presentation (5 pts.). Prepare presentation slides (PPT or PDF) and make a 10-15 min presentation of your project. Every team member should present his/her work as a part of the project.

Submission of the final project: Submit the final project report as Word, HTML or PDF documents through CCSU pipeline > Vista Courses > CS-385. The submission must inlcude the following items:

1. The report file with a general description of the machine architecture, diagrams for the major components, instruction set and format, and description of each major component. The report should also inlcude:
• The test program with comment showing the result that each instruction produces and Verilog simulation output that matches these results. Follow the directions in section Testing above.
• The Verilog source code with comment.
2. The presentation slides (PPT or PDF)

CS385 Midterm Test (maximal grade 20 points)

CS385 Final Exam (maximal grade 25 points)