CS 354 - Digital Systems Design

Fall-2007

Catalog data: Prereq.: CS 254 and MATH 218. PHYS 338 must be taken concurrently by those students whose program requires PhYS 338. An introduction to the analysis and design of digital systems in terms of logical and sequential networks. Various minimization techniques are studied.

Prerequisites: CS 254 and MATH 218

Description:  This course teaches how to design digital circuits at the gate level.  Students will analyze and design circuits with pencil and paper, and with a circuit design software. Students will learn and use Boolean algebra to design digital circuits without feedback, and characteristic tables and excitation tables to analyze the behavior of flip-flops. The design of circuits with feedback will be discussed through the use of  finite state machines. At the end, students will use their knowledge to design a simple computer central processing unit (CPU).

Course objectives: Upon successful completion of the course the student will be able to:

• Understand the basics of Boolean algebra
• Use minimization techniques to implement Boolean functions by logic gates
• Implement basic combinational circuits as adders, multiplexers, encoders and decoders
• Understand the basics of finite state machines
• Understand the basics of synchronous sequential logic (flip-flops)
• Implement clocked sequential circuits as registers, counters and memory devices
• Use a digital simulator and HDL to implement digital circuits
• Implement simple ALU and CPU

Required software: Digital circuit design and simulation software.

• Digital Works 2.0 (freeware, available from  http://www.cs.ccsu.edu/~markov/ccsu_courses/digwork.zip)
• Verilog HDL (book CD)
• Icarus Verilog (freeware, available from http://www.icarus.com/eda/verilog/).

Assignments and tests: Reading and problem assignments are listed below. Problems are to be done, but do not need to be handed in. Some of the problems will be worked in class. There will be 2 tests and a final exam. The tests will include questions from the textbook, questions from the lectures, and questions from the assigned projects.

Projects:  There will be 3 projects requiring the use of a digital simulator. The projects with their due dates are listed below (the project descriptions are given on separate pages).

Grading: The final grade will be based on projects (60%), quiz and tests (25%), and the final exam (15%), and will be affected by classroom participation, conduct and attendance. The letter grades will be calculated according to the following table:
 

A	A-	B+	B	B-	C+	C	C-	D+	D	D-	F
95-100	90-94	87-89	84-86	80-83	77-79	74-76	70-73	67-69	64-66	60-63	0-59

Honesty policy: It is expected that all students will conduct themselves in an honest manner (see the CCSU Student handbook), and NEVER claim work which is not their own.  Violating this policy will result in a substantial grade penalty, and may lead to expulsion from the University.  However, students are allowed to discuss projects with others and receive debugging help from others.

Tentative schedule of classes, assignments and tests

1. Basic components of the computer and its implementation: from instructions to gates. Lecture slides in PowerPoint
2. Boolean algebra: basic definitions, theorems and properties. Read 2-1 -- 2-3.
3. Boolean functions. Read 2-4.
4. Canonical and standard form of Boolean functions. Read 2-5.
5. Logic operations and logic gates. Read 2-6 -- 2-8.
6. Review of Chapter 2. Problems 2-1 -- 2-6, 2-8 -- 2.11, 2-14, 2-16 -- 2-19, 2-21.
7. September 26: Quiz 1 (Chapter 2, 5 pts.)
8. Simplification of Boolean functions: the map method. Read 3-1.
9. Four and five variable maps. Read 3-2, 3-3, 3-4.
10. NAND and NOR implementation of boolean functions. Read 3-5, 3-6.
11. Other implementations of boolean functions. Read 3-7, 3-8.
12. Review of Chapter 3. Problems: 3-1 -- 3-6, 3-8, 3-9, 3-10, 3-12, 3-13, 3-15, 3-16, 3-17, 3-19, 3-21, 3-24.
13. October 15: Test 1 (Chapters 2 and 3).
14. Basics of Verilog HDL and Digital Works. Read 3-9.
15. Combinational logic: analysis, design, code conversion, adders, subtractors. Read 4-1 -- 4-4. Chapter 4 figures.
16. Carry lookahead, binary adder-subtractor, overflow. Read 4-4.
17. October 29: Project 1 due
18. BCD adder, multiplier and comparator. Read 4-5, 4-6, 4-7.
19. Decoders, encoders and multiplexers. Read 4-8, 4-9, 4-10.
20. Read-only memory and PLA. Read 7-5, 7-6.
21. November 12: Test 2 (Chapter 4, ROM, PLA). Review problems: 4-9, 4-10, 4-11, 4-23, 4-25, 4-27, 4-28, 4-31, 4-32, 7-17, 7-18, 7-19, 7-20.
22. Designing an ALU
23. Using HDL to design combinational circuits. Read 4-11.
24. Project 2 due. Synchronous sequential logic: flip-flops. Read 5-1, 5-2, 5-3.
25. Designing a CPU.
26. Analysis of clocked sequential circuits: finite state machines, Turing machines. Read 5-4.
27. Designing clocked sequential circuits. Read 5-7. Problems: 5-6, 5-7, 5-10, 5-16, 5-19, 5-20.
28. Register and counters. Read 6-1, 6-2, 6-3, 6-4. Problems: 6-3, 6-4, 6-6, 6-9(a), 6-10, 6-17, 6-19, 6-27, 6-28.
29. Random access memory. Read 7-1, 7-2 (without HDL), 7-3.
30. Final Exam
31. Project 3 due

Boolean algebra: basic definitions, theorems and properties

A little history: George Boole

Axioms of Boolean algebra (set of elements B, two binary operators: + and .):

1. Closure
• w.r.t. +
• w.r.t. .
2. Identity element
• w.r.t. + denoted by 0: x+0=0+x=x
• w.r.t. . denoted by 1: x.1=1.x=x
3. Commutative law
• w.r.t. +: x+y=y+x
• w.r.t. .: x.y=y.x
4. Distributive law
• over +: x.(y+z)=(x.y)+(x.z)
• over .: x+(y.z)=(x+y).(x+z)
5. Complement: for every x there exists x', such that:
• x+x'=1
• x.x'=0
6. There exist at least two distinct elements x, y in B.

Defining a boolean algebra:

1. Show the elements of B
2. Show the rules of the operators + and .
3. Show that the axioms are satisfied
4. Example of a Boolean Algebra: For any set A, the subsets of A form a Boolean algebra under the operations of union, intersection and complement.

Binary logic (two-valued Boolean algebra):

1. B={0,1}
2. +  =  OR, . = AND, ' = NOT (truth tables)
3. Closure
4. Identity: 0 for + and 1 for .
5. Commutative law: see the truth tables
6. Distributive law: show by a truth table
7. Complement: show by a truth table and by the complement table
8. There are two distinct elements in B: 0 and 1

Basic theorems

1. x+x=x, x.x=x
2. x+1=1, x.0=0
3. (x')'=x (involution)
4. x+(y+z)=(x+y)+z, x.(y.z)=(x.y).z (associativity)
5. (x+y)'=x'.y', (x.y)'=x'+y' (DeMorgan's law)
6. x+xy=x, x.(x+y)=x (absorption)

Boolean functions

• algebraic expression - infinite number of expressions for a single boolean function.
• truth table - unique representation.

F1 = xyz'
F2 = x + y'z
F3 = x'y'z + x'yz + xy'
F4 = xy' + x'z
 

x     y     z	F1  F2  F3  F4
0     0     0  0     0     1  0     1     0  0     1     1  1     0     0  1     0     1  1     1     0  1     1     1	0   0   0   0   0   1   1   1  0   0   0   0   0   0   1   1   0   1   1   1   0   1   1   1   1   1   0   0   0   1   0   0

Implementing a Boolean function in Logic Gates (AND, OR, NOT)

• Using the algebraic form:
• literal: an input to a logic gate
• term: logic gate
• term and literal minimization
• Using truth table - first transform into algebraic form, sum of products

1. truth tables for result and carryout
2. transform into sum of products
3. build the logic diagram

• minimization of literals
• complement of a function, DeMorgan's theorem for more than two variables (dual of the function and complement each literal):
• (A+B+C+D+...)' = A'B'C'D'+...
• (ABCD...)' = A'+B'+C'+D'+...

1. x+x'y = (x+x')(x+y) = 1(x+y) = x+y

2. x(x'+y) = xx'+xy = 0+xy = xy

3. x'y'z+x'yz+xy' = x'z(y'+y)+xy' = x'z+xy'

4. xy+x'z+yz = xy+x'z+yz(x+x') = xy+x'z+xyz+x'yz = xy(1+z)+x'z(1+y) = xy+x'z

5. (x+y)(x'+z)(y+z) = (x+y)(x'+z)

Canonical and standard form of Boolean functions

Minterms and maxterms for three variables

x   y   z	Minterms	Maxterms
0   0   0	x'y'z'        m0	x + y + z      M0
0   0   1	x'y'z         m1	x + y + z'     M1
0   1   0	x'yz'         m2	x + y'+ z      M2
0   1   1	x'yz          m3	x + y'+ z'     M3
1   0   0	xy'z'         m4	x'+ y + z      M4
1   0   1	xy'z          m5	x'+ y + z'     M5
1   1   0	xyz'          m6	x'+ y'+ z      M6
1   1   1	xyz           m7	x'+ y'+ z'     M7

2. Representing Boolean functions (truth table) by a sum of minterms or by a product of maxterms
 

x     y     z	F1    F1'
0     0     0   0     0     1   0     1     0   0     1     1   1     0     0   1     0     1   1     1     0   1     1     1	0     1  1     0   0     1   0     1   1     0   0     1  0     1   1     0

F1 = x'y'z + xy'z' + xyz = m1 + m4 + m7

F1'= x'y'z' + x'yz' + x'yz + xy'z + xyz'

(F1')' = F1 = (x+y+z)(x+y'+z)(x+y'+z')(x'+y+z')(x'+y'+z) = M0.M2.M3.M5.M6

Alternative notation: F1 = Sum(1,4,7)

3. Canonical form (sum of minterms or product of maxterms) of Boolean functions

• We have  2^(2^n) functions of n variables.
• Transforming into sum of minterms:
• From algebraic form directly (using distributive law and ANDing (x+x') if x is missing).
• Example: F = a + b'c = ... = Sum(1,4,5,6,7)
• Using a truth table
• Transforming into product of maxterms: using distributive law and ORing xx'if x is missing).
• Example: F = xy + x'z = ... = Prod(0,2,4,5)

F1=Sum(1,4,7)
F1'=Sum(0,2,3,5,6)
F1=(F1')'=(Sum(0,2,3,5,6))'=Prod(0,2,3,5,6)

4. Standard form - sum of products or product of sums not necessarily containing all variables in the individual terms

Logic operations and logic gates

2. Algebraic forms of the 16 functions of 2 variables (ppt, ps)

3. Digital Logic gates and their implementation:

1. AND
2. OR
3. Inverter
4. Buffer
5. NAND
6. NOR
7. XOR
8. XNOR

• AND and OR: simple cascading
• 3-input NOR and NAND: not associative, change the definition to (x+y+z)' and (xyz)'
• Multiple input XOR and XNOR: associative, change the definition to "odd number of 1's"

• Small-scale integration (SSI): < 10
• Medium-scale integration (MSI): 10-100
• Large-scale integration (LSI): 100-1000
• Very large-scale integration (VLSI): >1000

Review of Chapter 2

1. Boolean algebra: basic definitions, theorems and properties
2. Boolean functions.
3. Canonical and standard form of Boolean functions.
4. Logic operations and logic gates
5. Implementation of the Boolean functions in logic gates:
• AND, OR, NOT
• NAND
6. Example: three-input majority function
• truth table
• sum of minterms, product of maxterms
• simplification
• AND, OR, NOT implementation
• NAND implementation

Simplification of Boolean functions - the map method

Two-variable map (properties)
 

m0	m1
m2	m3

x \ y	0	1
0	x'y'	x'y
1	xy'	xy

Examples:

xy

	1

x+y = x(y+y')+y(x+x') = xy+xy'+yx+yx' = xy+xy'+yx'

	1
1	1

(x+y)' = x'y'

1

Three-variable map (note the sequence)
 

m0	m1	m3	m2
m4	m5	m7	m6

x \ yz	00	01	11	10
0	x'y'z'	x'y'z	x'yz	x'yz'
1	xy'z'	xy'z	xyz	xyz'

Example: a + b'c = ... = Sum(1,4,5,6,7)

1
1	1	1	1

2. Simplification using maps (minimization of the number of terms)

• Adjacent squares (including m0 and m2, m4 and m6). Example: Sum(3,4,6,7) = xz'+yz
• 1 square - a term with 3 literals
• 2 adjacent squares - a term with 2 literals
• 4 adjacent squares - a term with 1 literal
• 8 adjacent squares - constant function 1
• Using adjacent squares more than once. Example: Sum(0,2,4,5,6) = z'+xy'
• Using a standard form (sum of product) - representing a product as adjacent squares. Example: x'z+x'y+xy'z+yz

x'y+x'y' =  m0+m1 = x' = M2.M3 = x'

1	1
0	0

Example: F(A,B,C,D) = Sum(0,1,2,5,8,9,10)

Four and five variable maps

Example 1: Sum(0,1,2,4,5,6,8,9,12,13,14) = y'+w'z'+xz'

wx\yz	00	01	11	10
00	1	1		1
01	1	1		1
11	1	1		1
10	1	1

Example 2: Sum(0,1,2,6,8,9,10) = x'y'+x'z'+w'yz'

wx\yz	00	01	11	10
00	1	1		1
01				1
11
10	1	1		1

2. A systematic approach to combining adjacent squares - prime implicants (max number of squares)

Example 3: Sum(0,2,3,5,7,8,9,10,11,13,15)

wx\yz	00	01	11	10
00	1		1	1
01		1	1
11		1	1
10	1	1	1	1

1. Essential prime implicant for m5, m7, m13, m15: xz
2. Essential prime implicant for m0, m2, m8, m10: x'z'
3. Prime implicants for m3, m9, m11: yz, x'y, w,z, wx'

4. The tabulation method (optional)

4.1. Determination of prime implicants

Example 1: F = Sum(0,1,2,8,10,11,14,15)
 

w x y z	w x y z	w x y z
0   0 0 0 0 * ---------------  1   0 0 0 1 *   2   0 0 1 0 *   8   1 0 0 0 * ---------------  10  1 0 1 0 *  ---------------  11  1 0 1 1 *   14  1 1 1 0 *  ---------------  15  1 1 1 1 *	0,1    0 0 0 -   0,2    0 0 - 0 *   0,8    - 0 0 0 * ------------------  2,10   - 0 1 0 *   8,10   1 0 - 0 *  ------------------  10,11  1 0 1 - *  10,14  1 - 1 0 * ------------------  11,15  1 - 1 1 *  14,15  1 1 1 - *	0,2,8,10     - 0 - 0   0,8,2,10     - 0 - 0 ----------------------  10,11,14,15  1 - 1 -   10,14,11,15  1 - 1 -

F = w'x'y' + x'y' + wy

1. Compare to the map method (same implicants)
2. Decimal comparison (difference by a power of 2)
3. Example 2: F = Sum(1,4,6,7,8,9,10,11,15)
• Tabulation: F=x'y'z + w'xz' + w'xy + xyz + wyz + wx'
• Map: F=x'y'z + w'xz' + xyz + wx'

1. Include all essential prime implicants (covering a single term): (1,9), (4,6), (8,9,10,11)

Choose minimal number of prime implicants: (7,15)

NAND and NOR implementation of boolean functions

• Useful graphic symbols:
• NAND or Invert-OR
• NOR or Invert-AND
• NAND-NAND (two level) implementation of Boolean functions. Example: F=xy+x'y'z'+x'yz'
1. Simplify the function (sum of products)
2. A NAND gate for each term (first level)
3. A single NAND gate at the second level with inputs coming from the outputs of the first level NAND's
• NOR-NOR implementation - the dual of the NAND-NAND
• Example: F=xy+x'y'z'+x'yz'. Implement F and F' by NAND-NAND, NOR-NOR and inverted the output.
• Incompletely specified functions (don't-care conditions). Example: F(a,b,c,d) = Sum(1,3,7,11,15), D(a,b,c,d) = Sum(0,2,5)
• Multilevel NAND implementation. Example: F=(AB'+A'B)(C+D')
1. Create an AND-OR multilevel implementation
2. Convert AND gates into NAND gates by inserting bubbles along the output.
3. Convert OR gates into NAND gates  (inserting bubbles at the inputs if necessary)
4. Remove all pairs of bubbles along the same line.
5. Replace the remaining bubles with one-input NAND gates
• Multilevel NOR implementation. Example: F=(AB'+A'B)(C+D')

Other implementations of boolean functions

• Nondegenerate forms of two level implementations:
• NAND-NAND
• NOR-NOR
• NAND-AND, AND-NOR (AND-OR-INVERT)
• OR-NAND, NOR-OR (OR-AND-INVERT)
• XOR function (difference)
• Properties
• AND-OR-NOT implementation
• NAND implementation
• Odd function
• XOR with more than two inputs
• implementation by cascading XOR's
• Parity checking

Basics of HDL and using Verilog and Digital Works

1. Example: implement a 3-input XNOR.
• F(A,B,C) = A XNOR B XNOR C
2. Digital Works:
• Create a Macro for XNOR (Macro Tags, Template Editor and Associate with Tag)
• Use the XNOR marco to design the circiut (Embed Macro)
3. Icarus Verilog
• Write the Verilog source file: 4-bit-adder.vl
• Compile:
C:\CS354\HDL>iverilog -o out 4-bit-adder.vl
• Run:
C:\CS354\HDL>vvp out
0000 0000 0 0000 0                   0
0000 0001 1 0010 0                  10
0001 0111 1 1001 0                  20
1111 0000 1 0000 1                  30

Combinational logic

1. Two types of logic circuits:
• Combinational logic (set of m Boolean functions of n variables), example: 7-segment LED display.
• Sequential (output are determined not only by the inputs, but also by internal states).
2. Analysis of digital circuits:
• Combinational or sequential? (no memory elements, no feedback)
• Determine the Boolean function
3. Design procedure
• Determine the number of inputs and outputs
• Derive the truth table
• Simplify the boolean function
• Draw the logic diagram
• Code conversion example: 3-bit 2's complementer
4. Adders: 0+0=0, 0+1=1, 1+0=1, 1+1=10.
• 1-bit half-adder: add two bits (x, y) and produce sum (S) and carry (C).
• Separate circuit implementation: C=xy, S=xy'+x'y (XOR).
• Sharing components implementations: C=xy, S=(C+x'y')'; C=(x'+y')', S=(x+y)(x'+y').
• 1-bit full-adder: add two bits and the carry from previous digit (x, y, z) and produce sum (S) and carry (C).
• Direct implementation: truth table, sum of minterms (C=xy+xz+yz, S=x'y'z+x'yz'+xy'z'+xyz).
• Cascading two half adders: S = add(add(x,y),z), C = C1+C2.
• Hierarchical design: 4-bit adder by cascading 4 1-bit adders.
5. Subtractors: 0-0=0(B=0), 0-1=1(B=1), 1-0=1(B=0), 1-1=0(B=0).
• Half-subtractor: subtract two bits and produce result and borrow.
• Full-subtractor: subtract two bits taking into account a borrow from the previous digit.

Carry lookahead, binary adder-subtractor, overflow, BCD adder

1. n-bit binary adder
• direct implementation: truth table with 2^(n+1) rows
• hierarchical implementation: cascading n 1-bit adders (serial, parallel)
2. Adder-subtractor (two's complement numbers)
3. Carry propagation (delay) and carry look-ahead logic
• carry propagate:  Pi = Ai xor Bi
• carry generate: Gi = Ai.Bi
• carry look-ahead logic: Ci+1 = Gi + Pi.Ci
• 4-bit adder with carry look-ahead: 4 half adders (xor, and) + carry look-ahead + 4 xor's
4. Detecting overflow:
• Overflow(A3, B3, S3)
• Overflow(C3,C4) = C3 XOR C4.

1. BCD adder: 4-bit adder + correction logic (if sum>1010 then add 0110 and produce decimal carry)
2. Binary multiplier
3. Magnitude comparator

Decoders, encoders and multiplexers

2. NAND implementation: inverted outputs and  enable (E) input
 

E x y	D0  D1  D2  D3
1 X X   0 0 0   0 0 1   0 1 0   0 1 1	1   1   1   1   0   1   1   1   1   0   1   1   1   1   0   1   1   1   1   0

3. Decoders/Demultiplexers

4. Cascading decoders by using the E input (4 X 16 made by two 3 X 8)

5. Implementing combinational circuits using decoders:

• the decoder outputs generate the minterms
• add an OR gate to produce the sum
• Example: full adder S(x,y,z)=Sum(1,2,4,7); C(x,y,z)=Sum(3,5,6,7)

6. Ambiguities: undefined inputs (more than one set to 1), D0 is a don't care input. Solution: priority encoder
 

D0  D1  D2  D3	x y V
0   0   0   0   1   0   0   0   X   1   0   0   X   X   1   0   X   X   X   1	X X 0  0 0 1  0 1 1   1 0 1   1 1 1

    Map: x=D2+D3, y=D1.D2'+D3 , V=D0+D1+D2+D3

7. Multiplexers (decoder + 1 input for each AND + second level OR)
 

s1  s2	Output
0   0   0   1   1   0   1   1	I0   I1   I2  I3

8. Implementing Boolean functions with a multiplexer: assigning functional value to each input (each combination of select lines)

9. Three-state gates. Implementing multiplexers with three-state gates: using a decoder for the three-state control inputs

Designing an ALU

1. The datapath and the ALU
2. ALU operations
• arithmetic and logic (add, sub, and, or)
• set on less than (slt)
3. Implementing subtraction:
• A+B = A+(-B)
• negation in two's complement: invert and add 1
4. Cascading 32 1-bit ALU's
5. Implementing subtraction - negation in two's complement: invert and add 1
1. Invert (multiplexer or XOR)
2. Add 1 - set the first carry to 1
6. Implementing slt: add Set and Less lines
7. Test for equality and completing the ALU

Using HDL to design combinational circuits

1. Example: 2x4 decoder

module decoder_gl (A,B,E,D);
   input A,B,E;
   output [0:3]D;
   wire Anot,Bnot,Enot;
   not
      n1 (Anot,A),
      n2 (Bnot,B),
      n3 (Enot,E);
   nand
      n4 (D[0],Anot,Bnot,Enot),
      n5 (D[1],Anot,B,Enot),
      n6 (D[2],A,Bnot,Enot),
      n7 (D[3],A,B,Enot);
endmodule
 
2. Example: 4-bit adder

// Description of half adder (see Fig 4-5b)
module halfadder (S,C,x,y);
   input x,y;
   output S,C;
//Instantiate primitive gates
   xor (S,x,y);
   and (C,x,y);
endmodule

//Description of full adder (see Fig 4-8)
module fulladder (S,C,x,y,z);
   input x,y,z;
   output S,C;
   wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the halfadder
    halfadder HA1 (S1,D1,x,y),
              HA2 (S,D2,S1,z);
    or g1(C,D2,D1);
endmodule

//Description of 4-bit adder (see Fig 4-9)
module _4bit_adder (S,C4,A,B,C0);
   input [3:0] A,B;
   input C0;
   output [3:0] S;
   output C4;
   wire C1,C2,C3;  //Intermediate carries
//Instantiate the fulladder
   fulladder  FA0 (S[0],C1,A[0],B[0],C0),
              FA1 (S[1],C2,A[1],B[1],C1),
              FA2 (S[2],C3,A[2],B[2],C2),
              FA3 (S[3],C4,A[3],B[3],C3);
endmodule
 

1. Example: 2x4 decoder

// Dataflow description of a 2-to-4-line decoder
module decoder_df (A,B,E,D);
   input A,B,E;
   output [0:3] D;
   assign D[0] = ~(~A & ~B & ~E),
          D[1] = ~(~A & B & ~E),
          D[2] = ~(A & ~B & ~E),
          D[3] = ~(A & B & ~E);
endmodule
2. Example: 4-bit adder

// Dataflow description of 4-bit adder
module binary_adder (A,B,Cin,SUM,Cout);
   input [3:0] A,B;
   input Cin;
   output [3:0] SUM;
   output Cout;
   assign {Cout,SUM} = A + B + Cin;
endmodule

//Behavioral description of 2-to-1-line multiplexer
module mux2x1_bh(A,B,select,OUT);
   input A,B,select;
   output OUT;
   reg OUT;
   always @ (select or A or B)
         if (select == 1) OUT = A;
         else OUT = B;
endmodule

//Behavioral description of 4-to-1- line multiplexer
//Describes the function table of  Fig. 4-25(b).
module mux4x1_bh (i0,i1,i2,i3,select,y);
   input i0,i1,i2,i3;
   input [1:0] select;
   output y;
   reg y;
   always @ (i0 or i1 or i2 or i3 or select)
            case (select)
               2'b00: y = i0;
               2'b01: y = i1;
               2'b10: y = i2;
               2'b11: y = i3;
            endcase
endmodule

4. Simulation by using test bench

//Stimulus for mux2x1_df.
module testmux;
  reg TA,TB,TS;  //inputs for mux
  wire Y;       //output from mux
  mux2x1_df mx (TA,TB,TS,Y);  // instantiate mux
     initial
        begin
              TS = 1; TA = 0; TB = 1;
          #10 TA = 1; TB = 0;
          #10 TS = 0;
          #10 TA = 0; TB = 1;
        end
     initial
      $monitor("select = %b A = %b B = %b OUT = %b time = %0d",
               TS, TA, TB, Y, $time);
endmodule

//Dataflow description of 2-to-1-line multiplexer
//from Example 4-6
module mux2x1_df (A,B,select,OUT);
   input A,B,select;
   output OUT;
   assign OUT = select ? A : B;
endmodule

Read-only memory and PLA

1. Implementing Boolean functions by using "programmable" decoders: minterms (decoder outputs) + OR gate (F). Array logic notation.
2. Read-only memory (ROM): (address space) X (word size), i.e. 2^n X m - sum of minterms
• Combinational logic implementation: decoder + fuses + OR gates (for each bit in the word), array logic notation for OR gates.
• Types of ROM: PROM, EPROM
3. Programmable logic array (PLA) - sum of products
• Simplify the functions for each output bit (using maps), e.g. F1=AB'+BC, F2=AC+BC
• Create a table with as many rows as the total number of products: 3 rows (AB', BC, AC)
• First column: product terms; second column: inputs; third column: outputs
• Using array logic notation. Example: CPU control
4. Example 1:
• F1(A,B,C)=SUM(0,1,2,4)
• F2(A,B,C)=SUM(0,5,6,7)
• Sum of product maps:
• F1 = A'B'+ A'C'+ B'C'
• F1'= AB + AC + BC
• F2 = AB + AC + A'B'C'
• F2'= A'C+ A'B + AB'C'
• Products: AB, AC, BC, A'B'C'
5. Example 2: PLA for BCD-to-seven-segment decoder (Problem 4-9).

Synchronous sequential logic: flip-flops

1. Combinational and sequential logic
2. Synchronous and asynchronous logic:
• Synchronous: behavior is determined by the inputs signals at discrete instants of time (clock pulses), clocked sequential circuits.
• Asynchronous: behavior is determined by the signals at any instant of time and the order in which the inputs change.
3. Memory elements (binary storage): flip-flops
4. Basic flip-flops (operate with signal level).
• RS latch
• D latch: RS latch with control (enable input)
5. Edge-Triggered flip-flops:
• respond to clock pulse edges: positive and negative
• master-slave D flip-flop: samples the input during the high clock pusle level, changes the state (Q) at negative edge.
6. JK and T flip-flops
• JK flip-flop - changes the state at the clock pulse edge, implemented with a D flip-flop:  D=JQ'+K'Q
• T flip-flop - complements its state:
• implemented with JK flip-flop: T=J=K (T=1 changes the state).
• implemented with D flip-flop: D = TQ' + T'Q = T XOR Q
7. HDL implementations: D_flip_flop.vl

Designing a CPU

1. Simple D flip-flop register
2. Operation of a CPU with a register type instructions
3. Instruction register
4. Register file (diagram in PDF)
5. Simple CPU datapath (diagram in PDF)

Analysis of clocked sequential circuits: finite state machines

1. Characteristic tables and equations: describing logical properties of a flip-flop. Using time for indexing the state output.

• RS flip-flop: Q(t+1)=SQ'(t)+R'Q(t)



S R	Q(t+1)
0 0   0 1   1 0   1 1	Q(t)   0   1   ?

• JK flip-flop: Q(t+1)=JQ'(t)+K'Q(t)



J K	Q(t+1)
0 0   0 1  1 0   1 1	Q(t)   0   1   Q'(t)

• D flip-flop: Q(t+1)=D



D	Q(t+1)
0   1	0   1

• T flip-flop: Q(t+1)=TQ'(t)+T'Q(t)



T	Q(t+1)
0  1	Q(t)   Q'(t)

• Logic diagram (D flip-flops)

A(t+1) = xA'(t)B(t) + xA(t)B'(t)
B(t+1) = xB'(t)
y = A(t)B(t)

State table: <present state> X <input> -> <next state>; <present state> -> <output>

3. Excitation tables
 
• RS flip-flop
 


Q(t) Q(t+1)	S R
0 0   0 1   1 0   1 1	0 X   1 0   0 1   X 0

•   JK flip-flop
 


Q(t) Q(t+1)	J K
0 0   0 1   1 0   1 1	0 X   1 X   X 1   X 0

4. State diagram - finite state machines
• Mealy model: <present state> X <input> -> <output> (output may change during the pulse)
• Moore model: <present state> -> <output>

5. Turing machines
• Alan Turing web page
• Turing machines
• A Turing Machine Applet

Designing clocked sequential circuits

2. State diagram (number of states -> number of flip-flops)

3. State table

 


Present state     A   B	Input    x	Next state    A   B	Output    y
0   0      0   0      0   1      0   1     1   0      1   0      1   1      1   1	0     1     0     1     0     1     0     1	0   0     0   1     0   1     1   0     1   0     1   1     1   1     0   0	0     0     0     0     0     0     0     1

 


Present state     A   B	Input    x	Next state    A   B	Flip-flop inputs    DA      DB
0   0      0   0      0   1      0   1     1   0      1   0      1   1      1   1	0     1     0     1     0     1     0     1	0   0     0   1     0   1     1   0     1   0     1   1     1   1     0   0	0       0    0       1     0       1     1       0     1       0     1       1     1       1     0       0

 


Present state     A   B	Input    x	Next state    A   B	Flip-flop inputs    TA      TB
0   0      0   0      0   1      0   1     1   0     1   0      1   1      1   1	0     1     0     1     0     1     0     1	0   0     0   1     0   1     1   0    1   0     1   1     1   1     0   0	0       0     0       1     0       0     1       1     0       0     0       1     0       0     1       1

7. Designing the combinational circuit (maps)

• D flip-flops:
• DA = xA'B + x'A + AB'
• DB = x'B + xB'
• T flip-flops:
• TA = xB
• TB = x

Register and counters

1. Registers: a group of binary cells (flip-flops) suitable for storing binary information
• Gated latch: accepting inputs during the clock pulse (C=1). Example: a group of D flip flops (Fig.6-1)
• Loading registers
• Parallel loading: providing access to all inputs at a time.
• C controlled loading (C acts as an enable  signal)
• Load control input
• applied to C. Example: D flip-flops with their C input anded with the load control input (delay of C).
• applied to all data inputs. Register with D flip-flops: load control used to switch between previous state and input (Fig. 6-2).
• Building sequential circuits with registers: equivalent to the D flip-flop implementation of sequential circuits with load control=1.
• Shift registers: using edge triggered D flip-flops, serial input, serial output (Fig.6-3), shift control, serial transfer  (Fig.6-4)
• Serial addition (Fig. 6-5).
2. Counters
• Synchronous counters (C applied to all flip-flops): flip-flops + combinational logic (see "Designing clocked sequential circuits")
• Ripple counters: series of complementing flip-flops with the output of each flip-flop connected to the C input of the next one.
• Binary ripple counter: T flip-flops or D flip-flops  (Fig.6-8).
• BCD ripple counter: state diagram (Fig. 6-9), logic diagram (Fig.6-10).

Random access memory

1. RAM block diagram: k address lines, n data input lines, n data output lines, Read/Write, Enable
2. Memory cell: RS flip-flop, Input, Output, Select, Read/Write, No CP used
3. Memory decoding. Example 4X2 RAM: 2X4 Decoder, 8 cells, two 4-input OR gates

Sample Problems for Test 1

• F = A’C’ + ABC + AC’to a sum of two terms
• F = (x’y’+ z)’+ z + xy + wz to a sum of three variables
• F = A’B(D’+ C’D) + B(A + A’CD) to one variable

Problem 3: Transform F into canonical form as a sum of minterms using a truth table or map.

• F = (xy + z)(y + xz)
• F = (A’+ B)(B + C’)

• F = (xy + z)(y + xz)
• F = (A’+ B)(B + C’)

• F = (xy + z)(y + xz)
• F = (A’+ B)(B + C’)

F = xy’z + x’y’z + w’xy + wx’y + wxy

Problem 7: Using the map method simplify in sum of products the following functions:

• F = x’z’+ y’z’+ yz’+ xy
• F = (A’+ B’+ D’)(A + B’+ C’)(A’+ B + D’)(B + C’+ D’)

• F = x’z’+ y’z’+ yz’+ xy
• F = (A’+ B’+ D’)(A + B’+ C’)(A’+ B + D’)(B + C’+ D’)

Review problems for the final exam

1. Simplification and implementation of Boolean functions (Chapter 3). Problems: 3-1 -- 3-6, 3-8, 3-9, 3-10, 3-12, 3-13, 3-15, 3-16, 3-17, 3-19, 3-21, 3-24.
2. Combinational circuits (Chapter 4). Problems: 4-9, 4-10, 4-11, 4-23, 4-25, 4-27, 4-28, 4-31, 4-32, 7-17, 7-18, 7-19, 7-20.
3. ROM and PLA (Chapter 7). Problems 7-17, 7-18, 7-19, 7-20.
4. Clocked sequential circuits (Chapter 5). Problems: 5-6, 5-7, 5-10, 5-16, 5-19, 5-20.
5. Register and counters (Chapter 6). Problems: 6-3, 6-4, 6-6, 6-9(a), 6-10, 6-17, 6-19, 6-27, 6-28.

Project 1

Building and testing basic combinational circuits by using Digital Works and Verilog HDL

Project 2

Building a 4-Bit ALU

Project 3

Building a 4-bit CPU