Take Final Exam on December 15 at 11am1pm

Project 3 is due on December 8

CS 354 - Digital Systems Design (Section 02)

Fall-2016

Classes: TR 10:50 am - 12:05 pm, Maria Sanford Hall 223
Instructor:  Dr. Zdravko Markov, 30307 Maria Sanford Hall, (860)-832-2711, http://www.cs.ccsu.edu/~markov/, e-mail: markovz at ccsu dot edu
Office hours: MW 4:30 pm - 5:45 pm, TR 9:00 am - 10:30 am

Catalog data: An introduction to the analysis and design of digital systems in terms of logical and sequential networks. Various minimization techniques are studied.

Prerequisites: CS 254 and MATH 218

Course Description:  This course teaches how to design digital circuits at gate level. It includes theoretical material on Boolean algebra and finite state machines, which are part of the fundamental Computer Science theory. Students analyze and design combinational and sequential circuits by using modern approaches to hardware simulation such as the Hardware Description Language. They use hierarchical approaches to create the basic components of the computer such as decoders, adders, registers and memories. At the end, students use their knowledge to design a simple central processing unit (CPU).

Course Learning Outcomes (CLO)

  1. Understand the basics of Boolean algebra
  2. Use minimization techniques to implement Boolean functions by logic gates
  3. Implement basic combinational circuits as adders, multiplexers, encoders and decoders
  4. Understand the basics of synchronous sequential logic and finite state machines
  5. Implement clocked sequential circuits as registers, counters and memory devices
  6. Use a Hardware Description Language (HDL) to design and implement digital circuits
  7. Design and implement simple ALU and CPU
CS 354 - Digital Design is part of the core CS program and is designed in accordance with the Program Educational Objectives (PEO) and the Student Outcomes (SO) as specified in the Department Mission Statement. The Course Learning Outcomes are used to assess the following Student Outcomes (SO): The CS 354 Course Learning Outcomes also support the following Student Outcomes (SO) which are part of the corresponding Program Educational Objectives (PEO): Required textbook: Morris Mano & Michael Ciletti, Digital Design, Fifth Edition, Prentice Hall, 2013.

Required software:

Class Participation: Regular attendance and active class participation is expected from all students. If you must miss a test, try to inform the instructor of this in advance. In case of missed classes and work due to plausible reasons (such as illness or accidents) limitted assistance will be offered. Unexcused absences will result in the student being totally responsible for the make-up process.

Assignments and tests: Reading and problem assignments are listed below. Problems are to be done, but do not need to be handed in. Some of the problems will be worked in class. There will be two tests, a quiz, and a final exam. The tests will include questions from the textbook, questions from the lectures, and questions from the assigned projects.

Projects:  There will be three projects requiring the use of the Verilog Hardware Description Language to implement and simulate digital circuits. The projects with their due dates are listed below in the class schedule (the project descriptions will be available in Blackboard Learn). All projects must be submitted through the course page in Blackboard Learn course management system available at https://ct-ccsu.blackboard.com/.

Grading: The final grade will be based on projects (55%), quiz and tests (25%), and the final exam (20%), and will be affected by classroom participation, conduct and attendance. All grades will be availabe in Blackboard Learn. The letter grades will be calculated according to the following table:
 
A A- B+ B B- C+ C C- D+ D D- F
95-100 90-94 87-89 84-86 80-83 77-79 74-76 70-73 67-69 64-66 60-63 0-59

Unexcused late submission policy: Assignments submitted more than two days after the due date will be graded one letter grade down. Projects submitted more than a week late will receive two letter grades down. No submissions will be accepted more than two weeks after the due date.

Honesty policy: The CCSU honor code for Academic Integrity is in effect in this class. It is expected that all students will conduct themselves in an honest manner and NEVER claim work which is not their own. Violating this policy will result in a substantial grade penalty, and may lead to expulsion from the University. You may find it online at http://web.ccsu.edu/academicintegrity/. Please read it carefully.

Students with disabilities: Students who believe they need course accommodations based on the impact of a disability, medical condition, or emergency should contact me privately to discuss their specific needs. I will need a copy of the accommodation letter from Student Disability Services in order to arrange class accommodations. Contact Student Disability Services, Willard Hall, 101-04 if you are not already registered with them. Student Disability Services maintains the confidential documentation of your disability and assists you in coordinating reasonable accommodations with your faculty.

Tentative schedule of classes, assignments and tests

Note: Dates will be posted for all classes, project and test due days (see also University Calendar). Additional material may be posted too. Check the schedule and the class pages regularly for updates!
  1. Aug 30: Basic components of the computer and its implementation: from instructions to gates. Run the 4-bit CPU (download it from Blackboard and use Digital Works). Read Chapter 1.
  2. Sep 1: Boolean algebra: basic definitions, theorems and properties
  3. Sep 6: Boolean functions
  4. Sep 8: Canonical and standard form of Boolean functions
  5. Sep 13: Logic operations and logic gates
  6. Sep 15: Review of Chapter 2
  7. Sep 20: Quiz (Chapter 2, max. grade: 5 pts.)
  8. Sep 22: Simplification of Boolean functions: the map method
  9. Sep 27: Four variable maps
  10. Sep 29: NAND and NOR implementation of boolean functions
  11. Oct 4: Other implementations of boolean functions
  12. Oct 6: Review of Chapter 3. Problems: 3.1 - 3.13, 3.15 - 3.17, 3.18 - 3.23, 3.27 - 3.30.
  13. Oct 11: Test 1 (Chapters 2 and 3, max. grade: 10 pts.)
  14. Oct 13: Basics of HDL and using Verilog and Digital Works
  15. Oct 18: Combinational logic: analysis, design, adders, subtractors, decimal adder
  16. Oct 20: Decoders, encoders and multiplexers
  17. Oct 25: Read-only memory and PLA
  18. Oct 27: Review of Chapter 4, ROM, and PLA. Problems: 4.9, 4.10, 4.11, 4.23, 4.25, 4.27, 4.28, 4.31, 4.32, 4.33, 7.17, 7.18, 7.19, 7.20.
  19. Oct 27: Project 1 due (max. grade: 10 pts.)
  20. Nov 1: Test 2 (Chapter 4, ROM, and PLA, max. grade: 10 pts.).
  21. Nov 3: No class
  22. Nov 8: Using HDL to design combinational circuits
  23. Nov 10: Designing an ALU
  24. Nov 15: Synchronous sequential logic: flip-flops
  25. Nov 17: Analysis of clocked sequential circuits: finite state machines, Turing machines
  26. Nov 22: Designing a CPU
  27. Nov 29: Project 2 due (max. grade: 20 pts.)
  28. Nov 29: Designing clocked sequential circuits
  29. Dec 1: Register and counters
  30. Dec 5-6: Take a Quiz for extra credit online in Blackboard
  31. Dec 6: Random access memory
  32. Dec 8: Review of Chapter 5. Problems: 5.6 - 5.10, 5-16, 5-19, 5-20.
  33. Dec 8: Project 3 due (max. grade: 25 pts.)
  34. Dec 15, 11am1pm: Final Exam (max. grade: 20 pts.)

Boolean algebra: basic definitions, theorems and properties

Reading: Book Sections 2.1 - 2.4
Exercises: Problems 2.1 - 2.3

Lecture Notes:

A little history: George Boole

Axioms of Boolean algebra (set of elements B, two binary operators: + and .):

  1. Closure
  2. Identity element
  3. Commutative law
  4. Distributive law
  5. Complement: for every x there exists x', such that:
  6. There exist at least two distinct elements x, y in B.

Defining a boolean algebra:

  1. Show the elements of B
  2. Show the rules of the operators + and .
  3. Show that the axioms are satisfied
  4. Example of a Boolean Algebra: For any set A, the subsets of A form a Boolean algebra under the operations of union, intersection and complement.

Binary logic (two-valued Boolean algebra):

  1. B={0,1}
  2. +  =  OR, . = AND, ' = NOT (truth tables)
  3. Closure
  4. Identity: 0 for + and 1 for .
  5. Commutative law: see the truth tables
  6. Distributive law: show by a truth table
  7. Complement: show by a truth table and by the complement table
  8. There are two distinct elements in B: 0 and 1
Duality principle: interchange + and . operators and replace 1's by 0's and 0's by 1's.

Basic theorems

  1. x+x=x, x.x=x
  2. x+1=1, x.0=0
  3. (x')'=x (involution)
  4. x+(y+z)=(x+y)+z, x.(y.z)=(x.y).z (associativity)
  5. (x+y)'=x'.y', (x.y)'=x'+y' (DeMorgan's law)
  6. x+xy=x, x.(x+y)=x (absorption)
Proofs by postulates and other theorems or by truth tables.


Boolean functions

Reading: Book Section 2.5
Exercises: Problems 2.4 - 2.9

Lecture Notes:

Defining Boolean functions Example 1: Boolean functions

F1 = xyz'
F2 = x + y'z
F3 = x'y'z + x'yz + xy'
F4 = xy' + x'z
 
 x     y     z  F1  F2  F3  F4
 0     0     0
 0     0     1
 0     1     0
 0     1     1
 1     0     0
 1     0     1
 1     1     0
 1     1     1
 0   0   0   0 
 0   1   1   1
 0   0   0   0 
 0   0   1   1 
 0   1   1   1 
 0   1   1   1 
 1   1   0   0 
 0   1   0   0 

Implementing a Boolean function in Logic Gates (AND, OR, NOT)

Example 2: Building 1-bit adder
  1. truth tables for result and carryout
  2. transform into sum of products
  3. build the logic diagram
Algebraic manipulations Example 3: Simplification (1<->2, 4<->5)

1. x+x'y = (x+x')(x+y) = 1(x+y) = x+y

2. x(x'+y) = xx'+xy = 0+xy = xy

3. x'y'z+x'yz+xy' = x'z(y'+y)+xy' = x'z+xy'

4. xy+x'z+yz = xy+x'z+yz(x+x') = xy+x'z+xyz+x'yz = xy(1+z)+x'z(1+y) = xy+x'z

5. (x+y)(x'+z)(y+z) = (x+y)(x'+z)


Canonical and standard form of Boolean functions

Reading: Book Section 2.6
Exercises: Problems 2.17 - 2.23, 2.30, 2.31

Lecture Notes:

1. Minterms and Maxterms

Minterms and maxterms for three variables
    x   y   z  Minterms  Maxterms
  0   0   0   x'y'z'        m0   x + y + z      M0 
  0   0   1   x'y'z         m1   x + y + z'     M1 
  0   1   0   x'yz'         m2   x + y'+ z      M2 
  0   1   1   x'yz          m3   x + y'+ z'     M3 
  1   0   0  xy'z'         m4   x'+ y + z      M4
  1   0   1   xy'z          m5   x'+ y + z'     M5 
  1   1   0   xyz'          m6   x'+ y'+ z      M6 
  1   1   1  xyz           m7   x'+ y'+ z'     M7

2. Representing Boolean functions (truth table) by a sum of minterms or by a product of maxterms
 
 x     y     z  F     F' 
 0     0     0 
 0     0     1 
 0     1     0 
 0     1     1 
 1     0     0 
 1     0     1 
 1     1     0 
 1     1     1 
 0     1
 1     0 
 0     1 
 0     1 
 1     0 
 0     1
 0     1 
 1     0

F = x'y'z + xy'z' + xyz = m1 + m4 + m7

F'= x'y'z' + x'yz' + x'yz + xy'z + xyz'

(F')' = F = (x+y+z)(x+y'+z)(x+y'+z')(x'+y+z')(x'+y'+z) = M0.M2.M3.M5.M6

Alternative notation: F = Sum(1,4,7), F = Prod(0,2,3,5,6)

3. Canonical form (sum of minterms or product of maxterms) of Boolean functions

4. Conversion between canonical forms

F(x,y,z)=Sum(1,4,7)
F'(x,y,z)=Sum(0,2,3,5,6)
F(x,y,z)=(F'(x,y,z))'=(Sum(0,2,3,5,6))'=Prod(0,2,3,5,6)

4. Standard form - sum of products or product of sums not necessarily containing all variables in the individual terms


Logic operations and logic gates

Reading: Book Section 2.7-2.9
Exercises: Problems 2.24 - 2.28

Lecture Notes:

1. The 16 Boolean functions of 2 variables (pdf)

2. Algebraic forms of the 16 functions of 2 variables (pdf)

3. Digital Logic gates and their implementation:

  1. AND
  2. OR
  3. Inverter
  4. Buffer
  5. NAND
  6. NOR
  7. XOR
  8. XNOR
4. Gates with multiple inputs and their implementation: 5. Integrated circuits

Review of Chapter 2

Reading: Book Chapter 2
Exercises: Problems 2.1 - 2.9,  2.17 - 2.28, 2.30, 2.31

Lecture Notes:

  1. Boolean algebra: basic definitions, theorems and properties
  2. Boolean functions. Algebraic simplification
  3. Canonical and standard form of Boolean functions.
  4. Logic operations and logic gates
  5. Implementation of the Boolean functions in logic gates:
  6. Example: three-input majority function

Simplification of Boolean functions - the map method

Reading: Book Sections 3.1, 3.2, 3.4
Exercises: Problems 3.1 - 3.3

Lecture Notes:

1. Map representation of Boolean functions

Two-variable map (properties)
 
 m0   m1 
 m2   m3 
 x \ y     0     1
 0    x'y'    x'y 
 1    xy'    xy

Examples:

xy
   
   1 

x+y = x(y+y')+y(x+x') = xy+xy'+yx+yx' = xy+xy'+yx'
   1 
 1   1 

(x+y)' = x'y'
 1   
   

Three-variable map (note the sequence)
 
  m0   m1   m3   m2
  m4   m5   m7   m6
  x \ yz    00   01   11   10
  0   x'y'z'   x'y'z   x'yz   x'yz'
  1   xy'z'   xy'z   xyz   xyz'

Example: a + b'c = ... = Sum(1,4,5,6,7)
 
 1    
 1   1  1   1 

2. Simplification using maps (minimization of the number of terms)

3. Product of sum simplification

x'y+x'y' =  m0+m1 = x' = M2.M3 = x'
 
 1  1
 0   0 

Example: F(A,B,C,D) = Sum(0,1,2,5,8,9,10)


Four variable maps

Reading: Book Section 3.3
Exercises: Problems 3.4 - 3.13

Lecture Notes:

1. Four-variable map
 
 m0   m1   m3  m2 
 m4  m5   m7  m6 
 m12   m13  m15  m14 
 m8   m9   m11   m10 

 
 wx\yz   00   01   11   10 
 00   w'x'y'z'   w'x'y'z   w'x'yz   w'x'yz' 
 01   w'xy'z'   w'xy'z   w'xyz   w'xyz' 
 11   wxy'z'   wxy'z   wxyz   wxyz' 
 10   wx'y'z'   wx'y'z   wx'yz   wx'yz' 

Example 1: Sum(0,1,2,4,5,6,8,9,12,13,14) = y'+w'z'+xz'
 wx\yz   00   01   11   10 
 00   1  1     1 
 01   1   1     1 
 11   1   1     1 
 10   1  1    

Example 2: Sum(0,1,2,6,8,9,10) = x'y'+x'z'+w'yz'
 wx\yz  00   01   11   10 
 00   1  1     1 
 01         1 
 11        
 10   1  1     1 

2. A systematic approach to combining adjacent squares - prime implicants (max number of squares)

Example 3: Sum(0,2,3,5,7,8,9,10,11,13,15)
 wx\yz  00  01  11  10
 00   1    1   1 
 01     1   1  
 11    1   1  
 10  1  1   1   1 

  1. Essential prime implicant for m5, m7, m13, m15: xz
  2. Essential prime implicant for m0, m2, m8, m10: x'z'
  3. Prime implicants for m3, m9, m11: yz, x'y, wz, wx'


3. The tabulation method (optional)

3.1. Determination of prime implicants

Example 1: F = Sum(0,1,2,8,10,11,14,15)
 
      w x y z         w x y z                w x y z 
 0   0 0 0 0 *
---------------
 1   0 0 0 1 *
 2   0 0 1 0 * 
 8   1 0 0 0 *
---------------
 10  1 0 1 0 * 
---------------
 11  1 0 1 1 * 
 14  1 1 1 0 * 
---------------
 15  1 1 1 1 * 
 0,1    0 0 0 - 
 0,2    0 0 - 0 * 
 0,8    - 0 0 0 *
------------------
 2,10   - 0 1 0 * 
 8,10   1 0 - 0 * 
------------------
 10,11  1 0 1 - *
 10,14  1 - 1 0 *
------------------
 11,15  1 - 1 1 *
 14,15  1 1 1 - *
 0,2,8,10     - 0 - 0 
 0,8,2,10     - 0 - 0
----------------------
 10,11,14,15  1 - 1 - 
 10,14,11,15  1 - 1 -
 
 

 

F = w'x'y' + x'y' + wy

  1. Compare to the map method (same implicants)
  2. Decimal comparison (difference by a power of 2)
  3. Example 2: F = Sum(1,4,6,7,8,9,10,11,15)
3.2. Selection of prime implicants
 
                      1  4  6  7  8  9  10  11  15 
 x'y'z  1,9           x              x
 w'xz'  4,6              x  x
 w'xy   6,7                 x  x
 xyz    7,15                   x                 x
 wyz    11,15                               x    x
 wx'    8,9,10,11                x  x  x   x
  1. Include all essential prime implicants (covering a single term): (1,9), (4,6), (8,9,10,11)
  2. Choose minimal number of prime implicants: (7,15)

NAND and NOR implementation of boolean functions

Reading: Book Sections 3.5, 3.6
Exercises: Problems 3.15 - 3.17, 3.19 - 3.23

Lecture Notes:


Other implementations of boolean functions

Reading: Book Sections 3.7, 3.8
Exercises: Problems 3.18, 3.27 - 3.30

Lecture Notes:


Basics of HDL and using Verilog and Digital Works

Reading: Book Section 3.9
Exercises: Problems 3.31, 3.32, 3.34 - 3.37

Lecture Notes:

Digital Works Verilog HDL
  1. Modules
  2. Gate-level description
  3. Test bench simulation
  4. Continuous assignment
  5. Example: implement a 3-input XOR,  F(A,B,C) = A XOR B XOR C

  6. // HDL Example (hierarchical design)
    //----------------------------------
    module my_xor(A,B,C);
       input A,B;
       output C;
       wire x,y,z;
       nand g1 (x,A,B),
            g2 (y,A,x),
            g3 (z,x,B),
            g4 (C,y,z);
    endmodule

    module my_xor3(A,B,C,D);
       input A,B,C;
       output D;
       wire x;
       my_xor XOR1 (A,B,x),
              XOR2 (x,C,D);
    endmodule

    module test_xor;
       reg A,B,C; // Reg for inputs
       wire D;    // Wire for outputs

       my_xor3 XOR3(A,B,C,D); // Instantiate my_xnor

       initial
         begin
           $display("Time A B C D");
               A=0; B=0; C=0;
           #10 A=0; B=0; C=1;
           #10 A=0; B=1; C=0;
           #10 A=0; B=1; C=1;
           #10 A=1; B=0; C=0;
           #10 A=1; B=0; C=1;
           #10 A=1; B=1; C=0;
           #10 A=1; B=1; C=1;
         end

       initial
         $monitor("%4d %b %b %b %b",$time,A,B,C,D);

    endmodule

  7. Icarus Verilog ( http://bleyer.org/icarus/).

Combinational logic: analysis, design, adders, subtractors, decimal adder

Reading: Book Sections 4.1 - 4.6
Exercises: Problems: 4.6, 4.9, 4.10, 4.11.
Slides: Chapter 4 figures

Lecture Notes:

  1. Two types of logic circuits:
  2. Analysis of digital circuits:
  3. Design procedure
  4. Adders: 0+0=0, 0+1=1, 1+0=1, 1+1=10.
  5. Subtractors: 0-0=0(B=0), 0-1=1(B=1), 1-0=1(B=0), 1-1=0(B=0).
  6. n-bit binary adder
  7. Adder-subtractor (two's complement numbers)
  8. Carry propagation (delay) and carry look-ahead logic
  9. Detecting overflow:
  10. BCD adder: 4-bit adder + correction logic (if sum>1010 then add 0110 and produce decimal carry)

Decoders, encoders and multiplexers

Reading: Book Section 4.9 - 4.11
Exercises: Problems: 4-23, 4-25, 4-27, 4-28, 4-31, 4-32, 4.33
Slides: Chapter 4 figures

Lecture Notes:

1. Decoders (n to 2^n) - minterm implementation (AND gates)
 
 x y z   D0  D1  D2  D3  D4  D5  D6  D7
 0 0 0 
 0 0 1
 0 1 0 
 0 1 1 
 1 0 0 
 1 0 1
 1 1 0 
 1 1 1 
 1   0   0   0   0  0   0   0 
 0   1   0   0   0   0   0   0 
 0   0   1   0   0   0   0   0
 0   0   0   1   0   0   0   0
 0   0   0   0   1   0   0   0 
 0   0   0   0   0   1   0   0 
 0   0   0   0   0   0   1   0 
 0   0   0   0   0   0   0   1

2. NAND implementation: inverted outputs and  enable (E) input
 
 E x y  D0  D1  D2  D3
 1 X X 
 0 0 0 
 0 0 1 
 0 1 0 
 0 1 1 
 1   1   1   1 
 0   1   1   1 
 1   0   1   1 
 1   1   0   1
 1   1   1   0 

3. Decoders/Demultiplexers

4. Cascading decoders by using the E input (4 X 16 made by two 3 X 8)

5. Implementing combinational circuits using decoders:

5. Encoders (OR gates)
 
 D0  D1  D2  D3  x y 
 1   0   0   0 
 0   1   0   0 
 0   0   1   0 
 0   0   0   1 
 0 0 
 0 1 
 1 0 
 1 1 

6. Ambiguities: undefined inputs (more than one set to 1), D0 is a don't care input. Solution: priority encoder
 
 D0  D1  D2  D3   x y V 
 0   0   0   0 
 1   0   0   0 
 X   1   0   0 
 X   X   1   0 
 X   X   X   1 
 X X 0
 0 0 1
 0 1 1 
 1 0 1 
 1 1 1 

    Map: x=D2+D3, y=D1.D2'+D3 , V=D0+D1+D2+D3

7. Multiplexers (decoder + 1 input for each AND + second level OR)
 
 s1  s2    Output
 0   0 
 0   1 
 1   0 
 1   1
 I0 
 I1 
 I2
 I3 

8. Implementing Boolean functions with a multiplexer: assigning functional value to each input (each combination of select lines)

9. Three-state gates. Implementing multiplexers with three-state gates: using a decoder for the three-state control inputs


Designing an ALU

Slides: Diagram in PDF
Reading: Patterson, Hennessy: Computer Organization and Design, 4th Edition: Appendix C.5 - Constructing a Basic Arithmetic Logic Unit
Programs: ALU4-behavioral.vl

Lecture Notes:

  1. The datapath and the ALU
  2. ALU operations
  3. Implementing subtraction:
  4. Cascading 32 1-bit ALU's
  5. Implementing subtraction - negation in two's complement: invert and add 1
    1. Invert (multiplexer or XOR)
    2. Add 1 - set the first carry to 1
  6. Implementing slt: add Set and Less lines
  7. Test for equality and completing the ALU

Using HDL to design combinational circuits

Reading: Book Section 4.12
Exercises: Problems: run the verilog programs shown below

Lecture Notes:

1. Gate-Level Modeling
  1. Example: 2x4 decoder

  2. module decoder_gl (A,B,E,D);
       input A,B,E;
       output [0:3]D;
       wire Anot,Bnot,Enot;
       not
          n1 (Anot,A),
          n2 (Bnot,B),
          n3 (Enot,E);
       nand
          n4 (D[0],Anot,Bnot,Enot),
          n5 (D[1],Anot,B,Enot),
          n6 (D[2],A,Bnot,Enot),
          n7 (D[3],A,B,Enot);
    endmodule
     
  3. Example: 4-bit adder

  4. // Description of half adder (see Fig 4-5b)
    module halfadder (S,C,x,y);
       input x,y;
       output S,C;
    //Instantiate primitive gates
       xor (S,x,y);
       and (C,x,y);
    endmodule

    //Description of full adder (see Fig 4-8)
    module fulladder (S,C,x,y,z);
       input x,y,z;
       output S,C;
       wire S1,D1,D2; //Outputs of first XOR and two AND gates
    //Instantiate the halfadder
        halfadder HA1 (S1,D1,x,y),
                  HA2 (S,D2,S1,z);
        or g1(C,D2,D1);
    endmodule

    //Description of 4-bit adder (see Fig 4-9)
    module _4bit_adder (S,C4,A,B,C0);
       input [3:0] A,B;
       input C0;
       output [3:0] S;
       output C4;
       wire C1,C2,C3;  //Intermediate carries
    //Instantiate the fulladder
       fulladder  FA0 (S[0],C1,A[0],B[0],C0),
                  FA1 (S[1],C2,A[1],B[1],C1),
                  FA2 (S[2],C3,A[2],B[2],C2),
                  FA3 (S[3],C4,A[3],B[3],C3);
    endmodule
     

2. Dataflow Modeling
  1. Example: 2x4 decoder

  2. // Dataflow description of a 2-to-4-line decoder
    module decoder_df (A,B,E,D);
       input A,B,E;
       output [0:3] D;
       assign D[0] = ~(~A && ~B && ~E),
              D[1] = ~(~A && B && ~E),
              D[2] = ~(A && ~B && ~E),
              D[3] = ~(A && B && ~E);
    endmodule
  3. Example: 4-bit adder

  4. // Dataflow description of 4-bit adder
    module binary_adder (A,B,Cin,SUM,Cout);
       input [3:0] A,B;
       input Cin;
       output [3:0] SUM;
       output Cout;
       assign {Cout,SUM} = A + B + Cin;
    endmodule
3. Behavioral Modeling

//Behavioral description of 2-to-1-line multiplexer
module mux2x1_bh(A,B,select,OUT);
   input A,B,select;
   output OUT;
   reg OUT;
   always @ (select or A or B)
         if (select == 1) OUT = A;
         else OUT = B;
endmodule

//Behavioral description of 4-to-1- line multiplexer
//Describes the function table of  Fig. 4-25(b).
module mux4x1_bh (i0,i1,i2,i3,select,y);
   input i0,i1,i2,i3;
   input [1:0] select;
   output y;
   reg y;
   always @ (i0 or i1 or i2 or i3 or select)
            case (select)
               2'b00: y = i0;
               2'b01: y = i1;
               2'b10: y = i2;
               2'b11: y = i3;
            endcase
endmodule

4. Simulation by using test bench

//Stimulus for mux2x1_df.
module testmux;
  reg TA,TB,TS;  //inputs for mux
  wire Y;       //output from mux
  mux2x1_df mx (TA,TB,TS,Y);  // instantiate mux
     initial
        begin
              TS = 1; TA = 0; TB = 1;
          #10 TA = 1; TB = 0;
          #10 TS = 0;
          #10 TA = 0; TB = 1;
        end
     initial
      $monitor("select = %b A = %b B = %b OUT = %b time = %0d",
               TS, TA, TB, Y, $time);
endmodule

//Dataflow description of 2-to-1-line multiplexer
//from Example 4-6
module mux2x1_df (A,B,select,OUT);
   input A,B,select;
   output OUT;
   assign OUT = select ? A : B;
endmodule


Read-only memory and PLA

Reading: Book Sections 7.5, 7.6
Exercises: Problems: 7.17, 7.18, 7.19, 7.20

Lecture Notes:

  1. Implementing Boolean functions by using "programmable" decoders: minterms (decoder outputs) + OR gate (F). Array logic notation.
  2. Read-only memory (ROM): (address space) X (word size), i.e. 2^n X m - sum of minterms
  3. Programmable logic array (PLA) - sum of products
  4. Example 1:
  5. Example 2: PLA for BCD-to-seven-segment decoder (Problem 4.9).

Synchronous sequential logic: flip-flops

Reading: Book Sections 5.1 - 5.4
Exercises: Problems: TBD
Slides: Chapter 5 figures

Lecture Notes:

  1. Combinational and sequential logic
  2. Synchronous and asynchronous logic:
  3. Memory elements (binary storage): flip-flops
  4. Basic flip-flops (operate with signal level).
  5. Edge-Triggered flip-flops:
  6. JK and T flip-flops
  7. HDL implementations:

  8.  

     

    module D_flip_flop(D,CLK,Q);
       input D,CLK;
       output Q;
       wire CLK1, Y;
       not  not1 (CLK1,CLK);
       D_latch D1(D,CLK, Y),
               D2(Y,CLK1,Q);
    endmodule

    module D_latch(D,C,Q);
       input D,C;
       output Q;
       wire x,y,D1,Q1;
       nand nand1 (x,D, C),
            nand2 (y,D1,C),
            nand3 (Q,x,Q1),
            nand4 (Q1,y,Q);
       not  not1  (D1,D);
    endmodule

    module test_D_flip_flop;
    reg D,C;
    wire Q;

    D_flip_flop D1(D,C,Q);

      initial
         begin
               D=0; C=0;
           #10 D=0; C=1;
           #10 D=0; C=0;
           #10 D=1; C=0;
           #10 D=1; C=1;
           #10 D=0; C=1;
         end

      initial
         $monitor("%d %b %b %b",$time,D,C,Q);

    endmodule


Designing a CPU

Lecture Notes:

  1. Simple D flip-flop register
  2. Operation of a CPU with a register type instructions
  3. Instruction register
  4. Register file (diagram in PDF)
  5. Simple CPU datapath (diagram in PDF)
  6. HDL implementation (CPU_Template.vl)

Analysis of clocked sequential circuits: finite state machines

Reading: Book Section 5.5
Exercises: Problems: 5.6 - 5.10
Slides: Chapter 5 figures

Lecture Notes:

1. Characteristic tables and equations: describing logical properties of a flip-flop. Using time for indexing the state output. 2. Sequential circuit examples (Figures 5.15- 5.20)
  • State table: <present state> X <input> -> <next state>; <present state> -> <output>
  •  Present state
         A B
     Input
       x
     Next state
        A B
     Output
       y
         0 0 
         0 0 
         0 1 
         0 1 
         1 0
         1 0 
         1 1 
         1 1 
       0 
       1 
       0 
       1 
       0 
       1
       0 
       1 
        0 0 
        0 1 
        0 0 
        1 0 
        0 0
        1 1 
        0 0 
        0 0 
       0 
       0 
       0 
       0 
       0 
       0 
       1 
       1

    Designing clocked sequential circuits

    Reading: Book Sections 5.7, 5.8
    Exercises: Problems: 5-16, 5-19, 5-20.
    Slides: Chapter 5 figures

    Lecture Notes:

    Example: if x=1 count 0,1,2,3,0,1,2,3,... ; if x=0 no change; output y=1 if state=3 and x=1, else y=0.

    1. Description of the circuit behavior: number of states, inputs, outputs, functionality.

    2. State diagram (number of states -> number of flip-flops)

    3. State table

       
       Present state
          A   B
       Input
         x
       Next state
         A   B
       Output
         y
          0   0 
          0   0 
          0   1
          0   1
          1   0 
          1   0 
          1   1 
          1   1
         0
         1
         0 
         1 
         0 
         1 
         0 
         1 
         0   0 
         0   1 
         0   1 
         1   0 
         1   0 
         1   1 
         1   1
         0   0 
         0 
         0 
         0 
         0 
         0 
         0 
         0 
         1 
    4. Excitation table (D flip-flops)
       
       Present state
          A   B
       Input
         x
       Next state
         A   B
       Flip-flop inputs
         DA      DB
          0   0 
          0   0 
          0   1 
          0   1
          1   0
          1   0 
          1   1 
          1   1
         0 
         1 
         0 
         1
         0 
         1 
         0 
         1 
         0   0 
         0   1 
         0   1 
         1   0
         1   0 
         1   1 
         1   1 
         0   0 
         0       0
         0       1 
         0       1 
         1       0 
         1       0 
         1       1 
         1       1 
         0       0 
    5. Excitation table (T flip-flops)
       
       Present state
          A   B
       Input
         x
       Next state
         A   B
       Flip-flop inputs
         TA      TB
          0   0 
          0   0 
          0   1 
          0   1
          1   0
          1   0 
          1   1 
          1   1
         0 
         1 
         0
         1
         0 
         1 
         0 
         1 
         0   0 
         0   1 
         0   1 
         1   0
         1   0 
         1   1 
         1   1 
         0   0 
         0       0 
         0       1 
         0       0 
         1       1 
         0       0 
         0       1 
         0       0 
         1       1 
    6. Block diagram: two flip-flops (D or T) + combinational circuit

    7. Designing the combinational circuit (maps)

    8. Counters: changing the state at each clock pulse, state bits as outputs, no inputs. Example: three-bit counter with T flip-flops.

    Register and counters

    Reading: Book Sections 6.1 - 6.4
    Exercises: Problems: 6.3, 6.4, 6.6, 6.9(a), 6.10, 6.17, 6.19, 6.27, 6.28.
    Slides: Chapter 6 figures

    Lecture Notes:

    1. Registers: a group of binary cells (flip-flops) suitable for storing binary information
    2. Counters

    Random access memory

    Reading: Book Sections 7.1, 7.2 (without HDL), 7.3
    Exercises: Problems: TBD

    Lecture Notes:

    1. RAM block diagram: k address lines, n data input lines, n data output lines, Read/Write, Enable
    2. Memory cell: RS flip-flop, Input, Output, Select, Read/Write, No CP used
    3. Memory decoding. Example 4X2 RAM: 2X4 Decoder, 8 cells, two 4-input OR gates

    Sample problems for Test 1 (Chapters 2 and 3)

    Problem 1: Simplify F algebraically to the indicated number of terms:
    Problem 2: Find the complement of an expression - see Problems 2.8, 2.20.


    Problem 3: Transform F into canonical form as a sum of minterms using a truth table or map.

    Problem 4: Transform F into canonical form as a sum of minterms algebraically.
    Problem 5: Transform F into canonical form as a product of maxterms (algebraically or by using a truth table/map). Problem 6: Simplify the function algebraically to a sum of three terms and implement the simplified function in standard logic (using AND, OR and NOT gates).

    F = xyz + xyz + wxy + wxy + wxy

    Problem 7: Using the map method simplify in sum of products the following functions. Show which map squares are covered by which term from the original function.

    Problem 8: Using the map method simplify in product of sums the following functions. Show which map squares are covered by which term from the original function.
    Problem 9: Implement the simplified functions from Problems 7 and 8 using two-level NAND and logic
    Problem 10: Implement the simplified functions from Problems 7 and 8 using two-level NOR and logic
    Problem 11: Implement in two-level NOR logic the function
    F(w,x,y,z)=SUM(0,1,2,3,4,8,9,12)
    Problem 12: Implement the function PROD(2,4) by using four NAND gates only.



    Review problems for the final exam

    1. Simplification and implementation of Boolean functions (Chapter 3). Problems: 3.1 - 3.13, 3.15 - 3.17, 3.18 - 3.23, 3.27 - 3.30
    2. Combinational circuits (Chapter 4). Problems: 4-9, 4-10, 4-11, 4-23, 4-25, 4-27, 4-28, 4-31, 4-32, 4.33
    3. ROM and PLA (Chapter 7). Problems 7-17, 7-18, 7-19, 7-20.
    4. Clocked sequential circuits (Chapter 5). Problems: 5.6 - 5.10, 5-16, 5-19, 5-20.
    5. Register and counters (Chapter 6). Problems: 6.3, 6.4, 6.6, 6.9(a), 6.10, 6.17, 6.19, 6.27, 6.28.

    Project 1 (10 pts.)

    Building and testing basic combinational circuits by using Verilog HDL

    Log on to Blackboard Learn to see and submit the project.


    Project 2 (20 pts.)

    Building a 4-bit ALU

    Log on to Blackboard Learn to see and submit the project.


    Project 3 (25 pts.)

    Building a 4-bit CPU

    Log on to Blackboard Learn to see and submit the project.